Sonum:

Intel Labs says it has successfully fabricated an indium-gallium-arsenide field-effect transistor (FET) atop a silicon substrate by integrating a high-k gate stack. As in Intel's advanced silicon transistors, the high-k dielectric allowed the necessary thinning of the gate oxide without increasing gate leakage.

http://www.eetimes.com/document.asp?doc_id=1172569

So, this is not new.

This is interesting! The EE Times article you quoted says (highlighting by me):

• Several hurdles have been cleared in the rush to commercialize III-V semiconductors on silicon substrates, including the ability to combine Si and InGaAs transistors on the same substrate and the architecting of both p- and n-type InGaAs devices.

This is the first time I am hearing that Intel would have "architected" p-type InGaAs devices (transistors). However, this was back in 2009. Another EE Times article, one of April this year, quotes semiconductor analyst David Kanter speaking about Intel's current secret plans (see http://www.eetimes.com/document.asp?doc_id=1326410):

• The new transistor structures will use two new materials – indium gallium arsenide (InGaAs) for n-type transistors and strained germanium for p-type devices, he said.

Oh, so the material for the p-type transistor has been replaced! It is no longer indium gallium arsenide (InGaAs), but strained germanium (Ge) instead. I would say that in 2009 they did sucessfully build an n-type InGaAs transistor and had an idea ("architected") how to do the same for a p-type transistor. However, they failed. Or why would they have made that replacement?

Seems we are still ahead of the curve. And we haven't discussed the optical stuff here, let alone the integration of optics and electronics or what POET has more than just transistors.