This is my favourite published description of POET memory. It's a bit technical in places, but built in to the summary is the story of how the current conception of PET's optical memory evolved during the SBIR research effort.

http://www.afsbirsttr.com/Include/Report/SummaryReport.aspx?pk=B87DCBB3-6910-4774-AE41-3EF24F72D4EC&type=TechMall

FTA:

"Original demonstrations of the thyristor memory function employed a single gating terminal to show the dynamic operation of the memory element. The thyristor enabled very high density (area determined essentially by the cross-point of an array) and negligible power consumption in the storage mode. Original conclusions were that the memory operation must be entirely electrical since emitters and detectors could not be formed with the size reduction of an ultra-small memory cell.

However, during the Phase I effort, the disk laser and disk detector configuration were applied to a novel memory cell implementation. With this innovation, the memory size becomes the smallest possible disk that can be designed, fabricated and contacted."

This is why POET boasts the density of DRAM and speed exceeding SRAM.

Reading another forum, I learned that DRAM could in principle be developed to be as fast as SRAM, but the cost per transistor would be prohibitive. Again we have a situation where POET not only matches and/or improves upon performance (not to mention improvements in energy consumption) but is actually cost effective aswell.

Assuming Taylor and his team are not mistaken, POET adoption for memory is a near certainty after POET is enabled for mass production.