Sounds like their only talking about the "the processes" used in manfacture and nothing to do with the superiority the POET chip will have over all others...

The collaboration gives the Poet team access to superior capability and diagnostics, allowing the Poet approach to start to scale to both 3" and 6" wafers with much larger device count and across wafer alignment. The fine features will then be merged with optical lithography and other procedures necessary to transition to a manufacturing environment. In addition, the effort will target line width reductions from 100-nm down to 40-nm which should enable Poet performance parameters to compete with present state-of-the-art processes. The reduction will be parallel to our efforts with our Synopsys TCAD collaboration.