@sulasailor

"In my view Graphene may be a significant competitor to the advantages Gallium Arsenide in the future. I wonder what Prof Taylor's view is?"

I can offer an outdated response to that very question. When we attended the 2011 AGM in Toronto we were all very concerned about the threat of silicon photonics developments by Intel and IBM (both seem to be sidelined, or were overhyped from the beginning), but also recent developments in graphene transistor technology.

I asked Taylor directly about graphene as a competitor, and his response was that "it's all about compatibility". At the time, I remember jumping to the wrong conclusion that Taylor felt graphene wouldn't play nice with other computer parts build for CMOS. This may in fact be true, as I have read that any contact between graphene and any other material can drastically alter its properties (such as electron/hole mobility).

Later after doing more reading I realized clearly that he was talking about compatibility with CMOS fab processes. POET is anticipated to be "bolt on" to existing CMOS fab facilities. So to add to what Andrea already rightfully pointed out, there's the economic side. I think graphene still seems to represent a total overhaul to the fab process for ICs, where POET will not only enable the continued use of current fab techniques, but it could possibly allow the use of exiting fabs which were considered out of date!

As many articles attest, each Si CMOS node requires a host of new and expensive fab techniques which enable feature size reduction. We are at the point where shrinking transistor gates do not bring the economic advantage in terms of number of transistors per unit area.

The curve is flat.