http://www.semiconductor.com/resourc...

"In its latest 16-Gbit MLC NAND flash device, Samsung has simplified the floor plan and architecture from the previous generation 65nm 8Gbit MLC NAND flash device," stated Young Choi, SI’s Technology Manager - Memory. "There are two row decoder areas, which split the memory array into four 4-Gbit arrays. Page buffers are now all consolidated in one side of the chip, as opposed to having two halves on either side of the memory array in the previous-generation product."

Multi level cell.....

For the previous 8Gbit devices...they split the levels... 4 and 4... with two row decoders and two opposed page buffers on each side.

For the new 16Gbit they split 8Gbit(4/4) on each side...with two row decoders for each side.....while consolidating the page buffers to one side.

IMO, there could possibly be cheating going on. I have written in the past the ability of e.Digital to orchestrate two separate cash buffers in an advanced streaming method to and from NAND flash devices..... This is, IMO, what is taking place above.

.IMO... through the multi page buffers above....they could be allowing for an advanced streaming of data for concurrent reads and writes, as described in the patents.

doni