https://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.htm&r=1&p=1&f=G&l=50&d=PTXT&S1=11,448,827&OS=11,448,827&RS=11,448,827
United States Patent |
11,448,827 |
Lam |
September 20, 2022 |
Wafer-level optoelectronic packaging
Abstract
A wafer-level optoelectronic packaging method includes fabricating a pre-singulated wafer. The pre-singulated wafer has a plurality of sub-mounts. A first sub-mount of the plurality of sub-mounts includes an optical waveguide formed on a substrate, a multi-layered sub-mount boundary wall that is formed on the optical waveguide, and a v-groove that is external to the sub-mount boundary wall. A plurality of optical dies are attached to the corresponding plurality of sub-mounts, such that each optical die is aligned to the optical waveguide of the corresponding sub-mount. A cap-wafer including a plurality of caps is attached to the pre-singulated wafer to obtain an encapsulated pre-singulated wafer. The encapsulated pre-singulated wafer is diced to obtain a plurality of optoelectronic packages. The optical waveguide of each optoelectronic package serves as an interconnection conduit between the corresponding optical die and an optical fiber placed in the corresponding v-groove.
Inventors: |
Lam; Yee Loy (Singapore, SG) |
Applicant: |
Name |
City |
State |
Country |
Type |
POET Technologies, Inc. |
San Jose |
CA |
US |
|
|
Assignee: |
POET Technologies, Inc. (San Jose, CA) |
Family ID: |
1000006570164 |
Appl. No.: |
16/860,615 |
Filed: |
April 28, 2020 |