By providing users with a so-called process design kit, which contains mask layout and accurate functional descriptions of the basic building blocks and more complex sub-circuits, users can design complex circuits without having to understand the underlying technology

I'm not totally clued up in the Poet tech. But this doesn't seem to be the same thing at all. It appears to be a more efficient way of designing pics, rather than wafer scale integration using an OI.

I can't see any talk of water scale intergration and testing. They appear still to be using a pick and place method for developing the IC. This will still require costly alignment techniques etc. Not sure how it overcomes the heat loss we hear about either.

Hopefully FJ or someone can confirm. But I wouldn't worry too much about this company