Shash, not sure how to say this any other way but that is not correct. It is  not  my understandinng. It is not surprising that even people who follow POET’s development closely could still be unclear about some aspects. The dielectric stack is deposited on 8 inch bulk silicon wafers (at low  temp,  low stress) which we were told was both at a lower cost and higher availability over silicon on insulator (SOI) wafers which are required for silicon photonics. This makes sense as the dielectric stack replaces optical functions that would normally require SOI. The InP dies are produced on 4 inch InP wafers which are flip chipped onto the processed silicon which have been coated with the dielectric. The dielectric stack is etched to produce both the mating features for  the active die (lasers and elements requiring optical  gain) and aligned and fixed to  the waveguides which provide filtering and passive requirements (high gain combined with low loss connectivity) . 

But to  answer the question. If 500 optical  engines fit  onto  an 8 inch silicon wafer (assuming each die  was 10mm X 5mm) which roughly fits with the diagram presented at the AGM with the dime over the 8 in wafer. Then a 12 inch wafer would fit 1200 optical engines. Sounds good  except one thing. I expect 12 inch wafer foundries are set up for much smaller and more advanced nodes than anything POET would  require. We are told that there is lots of  capacity available in 8in using the older nodes that POET requires. So again more cost savings by using lower cost capacity. It won’t always be that way though. As natural progression would have it 12in wafers will no doubt be used  in the future as higher node applications with imbedded  logic and memory are utilized on the same silicon substrate which will likely be in SOI wafers for more advanced electronic functions.