If that hasn't changed:

POET’S Near Term Solution

POET technology would allow the implementation of an optical interface as a single chip to connect existing CMOS processors. The optical interface chip would integrate the laser, modulator, modulator driver, detect or, receiver amplifiers, SERDES, CDR and PLL circuits monolithically. Both the DSP and the POET chip would be mounted face down in close proximity on a Si carrier that forms a single common plane. The carrier has a standard MT connector for a 12 channel fiber ribbon cable for optical I/O. The POET chip would connect to the fibers through a proprietary, (patented) mating technique. POET also connects to transmission lines (T/L's) on the Si carrier through standard solder bumps. The CMOS processor connects to the same T/L's with solder bumps. The assembly cost would be reduced substantially along with the power dissipation. The sizeable speed advantage of strained InGaAs quantum wells increases the bandwidth. Assigning one optical interface to each processor, processors on multiple carriers are connected optically by fiber. Alternately, waveguide patterns on the same Si carrier may connect one optical interface to the next, enabling multiple processors on the same Si carrier to be connected. The processor plus optical interface is the unit installed on a common PCB. With minimum feature sizes of 0.5μm, the transmitter power at 15Gb/s is estimated to be 4mW (0.27pJ/bit) delivering an optical power of 1mW in a chip area of 1.5x10 - 4mm2.

Correspondingly, the receiver power at 15Gb/s is estimated to be 6.3mW (0.42pJ/bit) receiving an optical power of 20μW in a chip area of 1.6x10 - 4mm2. Upon completion, the initial solution addresses the OE Interface requirements for both the military and commercial markets.