Watching the great talk of Dan I stepped over this speed issue again:

He is telling us a 5x speed advantage of Poetry vs Si at the same node size (which makes to me much sense, 25-50 GHz should be possible with our chips).

But he also mentions that one node size reduction results in a speed gain of about 20% (valid for Si as well as Poet).

Does this correlate with the speed advantage of 4 nodes (3 in power consumption)? 4x 20% is giving just double speed -at the same number of cores.

my assumption: this 4 nodes speed advantage is just a very careful, stealthy prediction. Once Poet will show real world speed results on 40nm, we will see a very positive surprise! Long before NRE. Or is my guess totally wrong?