They probaly want to see if GaAs can be properly scaled down. It is in unlikely the first chips on the market will be the smallest possible size. What room would there be for advancement if they made a chip at 15 nm or something?

They will probably be making chips far larger and reduce size every few years like with sillicon to create and have revenue for the next (few) decades.

If they didn't, they'd be needing superior technolgy then POET after a few years already. Even GaAs is susceptable to quantum anomalies at small sizes. Only difference is that sillicon at very small sizes is far inferior tho GaAs at far larger sizes. Shrink GaAs down at the same level sillicon is now (or smaller) and you will have the same problems as Sillicon.