"(b) coupling a cache memory to the primary memory, said cache memory providing temporary and volatile storage for at least one of the data segments;"
The above is what they all fear.... this would have to be the main crutch for Intel’s challenge of non-validly...based on past history.
Thing is, the RAM issue is there in writing.
To interface flash...e.Digital utilizes an SRAM sized to one data segment as proportioned by the operating system and the physical write properties of the flash it is utilizing.
With that, the SRAM can be sized small enough that the flash memory emulates as if it were a RAM resource.
Managing data with the patented operating system methods eliminates tremendous overhead compared to previous methods of data management.
Creating data in this manner happens in real time on the fly. This is important to NUNCHI where many types of data need to be created fast and on the fly. For the NUNCHI platform the output of this process does not have to transmit to a flash chip, it can be transmitted to a process on a server for additional processing and then turned around if needed.
Defendants are focusing on e.Digital not utilizing RAM in its methods, however e.Digital does implement RAM in a specific manner in relation to its operating system methods....where the RAM's use is not typical of prior methods for creating data and managing it.
e.Digitals gamble, and ours, was to wait for the physical properties of flash, specifically the write speeds of flash, to improve to a point that this method to interface flash would be possible….Where now, for similar considerations, we are waiting for the speed of networks to improve.
And here we are, flash can now write fast enough to emulate RAM...if utilizing e.Digitals patented process….
Without a doubt in my mind, a very broad base of the industry is well aware of what it means….especially Intel, as they actually got very close to e.Digital.
The only thing Intel is doing, IMO, they are killing time as best they can.
108 need be set free of the appeal….
doni
