Intel, Micron tip air-gap in NAND

SAN FRANCISCO - During the International Electron Device Meeting (IEDM) here, Intel Corp. and Micron Technology Corp. tipped more details about its 25-nm NAND process and disclosed a surprise: It has deployed the world’s first air-gap technology in a commercial chip product.

Intel and Micron have a joint NAND venture, dubbed IM Flash Technologies LLC. The companies already announced and shipped its 25-nm NAND parts. It has not disclosed the use of air-gap, which is reportedly used as a dielectric.

IM Flash has reportedly beat its rivals to the punch in air-gap. ''This is the first commercial use of air-gap technology,’’ said Dick James, an analyst with Chipworks.Many companies, including IBM and others, have also talked about devising air-gap.

In a paper at IEDM, Intel and Micron talked about a 64-Gb MLC device. The half-pitch of the cell is 24.5-nm in the WL (word line) direction and 28.5-nm in the BL (bit line) direction resulting in a cell size of 0.0028µm2.

''The cell is patterned using advanced pitch reduction techniques employing wet 193-nm lithography optimized to minimize line edge roughness and CD variation,’’ according to the paper.

''At a 25-nm dimension, a 5 percent CD variation is ~3 Si lattices. The AA trench depth cannot be scaled significantly because of the ~6V isolation requirements during inhibit, resulting in a 7:1 aspect ratio for the STI trench,’’ according to the paper.

''Any structural imbalance can lead to the AA bending resulting in displacement of the channel by as much as 10-nm for a 3-nm CD offset,’’ according to the paper. ''Controlling the structural bending is critical for achieving good electrical distributions of the cells in the NAND array. The aggressive WL pitch scaling leads to increased WL to WL capacitance as well as increased cell to cell interference.’’

Here’s the big surprise: ''An airgap is introduced between the WLs to overcome both these problems. An airgap is also used between the BLs,’’ according to the paper.