THIS IS VERY INTERESTING ! DUANE MORRIS ACCEPTED ALL EDIG CLAIMS AND PATENTS DESPITE KNOWING FOLLOWING EMBEDDED FLASH MEMORY PATENTS.TO ME IT MEANS THEY DID THOROUGH AND EXHAUSTING DUE DILLIGENCE BEFORE THEY SIGNED CONTRACT WITH EDIG. THAT MEANS A LOT WITH AN EXTRA ORDINARY CONFIDENCE ON OUR PATENTS VALIDITY.
Inventor(s)
Assignee
Application
No. 10403137 filed on 03/31/2003
Current US Class
257/315, With floating gate electrode 257/E21.682, With source and drain on same level and without cell select transistor (EPO) 257/E27.103, Electrically programmable ROM (EPO) 438/265, Oxidizing sidewall of gate electrode 438/279, Making plural insulated gate field effect transistors having common active region 438/283, Plural gate electrodes (e.g., dual gate, etc.) 438/303, Utilizing gate sidewall structure 257/326, With additional, non-memory control electrode or channel portion (e.g., accessing field effect transistor structure) 47/43, Props 365/185.01, FLOATING GATE 438/257, Having additional gate electrode surrounded by dielectric (i.e., floating gate) 438/261, Multiple interelectrode dielectrics or nonsilicon compound gate insulator 438/267, Including forming gate electrode as conductive sidewall spacer to another electrode 438/305, Plural doping steps 257/314, Variable threshold (e.g., floating gate memory device) 257/321, With thin insulator region for charging or discharging floating electrode by quantum mechanical tunneling 438/258, Including additional field effect transistor (e.g., sense or access transistor, etc.) 438/259, Including forming gate electrode in trench or recess in substrate 438/201, Including insulated gate field effect transistor having gate surrounded by dielectric (i.e., floating gate) 438/266 Having additional, nonmemory control electrode or channel portion (e.g., for accessing field effect transistor structure, etc.)
Field of Search
257/E21.682, With source and drain on same level and without cell select transistor (EPO) 257/E27.103, Electrically programmable ROM (EPO) 438/265, Oxidizing sidewall of gate electrode 438/279, Making plural insulated gate field effect transistors having common active region 438/283, Plural gate electrodes (e.g., dual gate, etc.) 438/303 Utilizing gate sidewall structure
Examiners
Primary: Nelms, David C.
Assistant: Tran, Mai-Huong
Attorney, Agent or Firm
US Patent References
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Claims
What is claimed is:
1. A flash memory cell comprising:
a substrate having a source region;
a floating gate structure disposed over the substrate and associated with the source region;
a source coupling enhancement structure covering an exposed portion of the floating gate structure and extending to the source region.
2. The flash memory according to claim 1, further comprising a control gate structure at least partially disposed over the floating gate structure, the control gate structure associated with a drain region of the substrate.
3. The flash memory cell according to claim 1, wherein the source coupling enhancement structure includes a capacitive dielectric film.
4. The flash memory cell according to claim 3, wherein the capacitive dielectric film comprises an oxide-nitride-oxide composite film.
5. The flash memory cell according to claim 3, wherein the source coupling enhancement structure further includes an electroconductive spacer.
6. The flash memory cell according to claim 2, wherein the floating gate and control gate structures comprise a split gate structure.
7. The flash memory cell according to claim 2, further comprising an intergate dielectric disposed between the floating and control gate structures.
8. The flash memory cell according to claim 1, wherein the substrate further includes an active region and an isolation region, the source region being disposed in the active region.
9. The flash memory cell according to claim 1, wherein the floating gate structure includes a dielectric film and an electroconductive film disposed over the dielectric film.
10. The flash memory cell according to claim 9, wherein the dielectric film comprises a silicon oxide film and the electroconductive film comprises a polysilicon film.
11. The flash memory cell according to claim 2, wherein the control gate structure includes a dielectric film and an electroconductive spacer.
12. The flash memory cell according to claim 11, wherein the dielectric film comprises a high temperature oxide film and the electroconductive spacer comprises a polysilicon spacer.
13. The flash memory cell according to claim 2, further comprising a channel region disposed between the source and drain regions.
14. The flash memory cell according to claim 1, further comprising a contact for applying voltages to the source region.
15. A method of fabricating a flash memory cell, the method comprising the steps of:
