The ACOTES project is an EU funded initiative to maximize the potential of parallel computing in chips, while extending the battery life of consumer devices. The aim is to develop technologies for longer lasting mobile phones or the ability to watch TV on mobile devices-without severe power drains.

"Although the amount of parallelism built into the chips is increasing, it is also introducing greater complexity for application programmers who are now being challenged with expressing the parallelism and prioritizing the way computing tasks and resources should be allocated," pointed out Dr. David Bernstein, manager of software and verification technologies at the IBM Research Lab in Haifa. According to Bernstein, ACOTES tools and methodologies will make it easier to program and develop applications that take maximum advantage of the chip's parallelism.

The IBM team working on ACOTES specializes in developing advanced optimizations for new compiler architectures for embedded systems. "Today's power hungry devices need the ability to exploit chips' full parallelism and new technological advances," notes Bernstein.

"ACOTES will re-define the power-performance ratio to achieve highly optimized and predictable battery lifetimes for mobile devices," explained Harm Munk, ACOTES project leader in NXP Semiconductors. "By getting more parts of the chip to work in parallel, ACOTES increases the utilization of contemporary and future parallel chip architectures. ACOTES will allow future parallel architectures to really flex their compute power muscles."

Most chips today incorporate the ability to run computing tasks in parallel, but very few actually make use of the full performance potential available. "If we could take a snapshot of a chip at work, we'd see that it contains both hot spots where computing is taking place, along with inactive areas that are not being used. ACOTES is geared towards helping chips reach a higher level of parallelism," added Munk.

ACOTES partners are in the midst of a three-year program at the end of which, their new tools are expected to take advantage of 90 percent of chip parallelism for selected applications - as opposed to the 40 percent or 50 percent being utilized today. The tools developed will be made available to the open source community as part of the GCC compiler.

In addition to NXP and IBM Haifa Research Lab, participants include STMicroelectronics; French research group INRIA; Universitat Politecnica de Catalunya, Spain; and Dutch chip group Silicon Hive.

Although previous attempts failed to create tools that automatically parallelized programs, ACOTES partners feel they are on the right track. "We will first develop a robust methodology for working manually and then regulate its automation in a sure step by step process," noted Munk. "We see this as a major first step that will shape an infrastructure upon which future projects and technologies can be built."