FPGA....programmable logic.

"ProASIC3 is still the as-close-to-SRAM-speed-as-flash-can-get family."

.........soon others will do the same.

IMO...if their utilizing memory of a serial matrix(NAND), in order for them to tie all the logic together within the flash,  stepping into the bounds of e.Digitals patented serial environment will be unavoidable.

Actel is pulling the trigger....Sandisk is doing the same. .........soon others will do the same.

 There will always be a place for status quo shadowed / paged processes to RAM resource. However, when it comes to battery powered processes, the paging becomes nothing more than a pass through process and flash will become the primary memory.

As far as I can tell...e.Digitals IP is the first to make it happen. IMO,  For any company that utilizes a cache combination in the same pass through manner e.Digital does,  will be infringing.

 Keep in mind, they also preform this process through multiple memory configurations simultaneously.

doni