Downsides
Ashwood, however, does admit to two downsides to his memory architecture. First, it is still just a paper design. He plans to work with licensees to implement his design on their memory arrays, but so far only a software simulation has been completed.

"I have fully developed the memory chip architecture, and I have run a software simulation to verify that it works, but so far I have not done a design at the electrical signal level—that kind of detail is dependent on who ends up licensing it," he said.

The second downside is that the parallel access overhead of the Ashwood memory architecture slightly slows down memory access times to individual memory cells—a disadvantage that is offset by its many parallel access channels, Ashwood said.

"For instance, if a NAND flash chip has an access time of 20 to 50 nanoseconds today, adding my architecture would increase that access time to 50 to 70 nanoseconds," he said. "But remember, during that time, 100 or more other memory retrieval operations could be in progress concurrently, yielding an effective access time of just a few nanoseconds per retrieval."

Late last year Ashwood filed a patent on his memory architecture, but because chipmakers could implement it before the patent is grated, he is choosing to keep most of the architecture secret until the patent is granted next year.