Somewhere around the 45- or 32-nanomter node, some industry observers believe floating gate NAND will peter out. Toshiba's idea, tipped at this week's VLSI Symposium in Japan, is to create pillars of stacked memory elements that pass vertically through layers of electrode material and utilize shared peripheral circuits.

The pillars would slot into holes etched through a stacked substrate, much in the same way that columns rise through floors of a building. Toshiba described it as a "multi-layer sandwich of gate electrodes and insulator films."

The pillars of silicon are lightly doped with impurities. The gate electrode wraps around the silicon pillar at even intervals, and a pre-formed nitride film for data-retention, based within a silicon-oxide-nitride-oxide-silicon (SONOS) structure, is set in each joint and serves as a NAND cell, the company said.

Officials at Toshiba were not immediately available for comment. So it remains unclear exactly when the company hopes to commercialize the technology, in which densities, or what challenges it still faces, such as endurance and comparable performance in read/write times.

The SONOS formula has been around for years and is currently being pursued by other companies such as Motorola Corp. and Cypress Semiconductor as a better means for embedding flash than the typical floating-gate structure.

Other companies are also tapping SONOS-like structures to breathe new life into discrete NAND. The commodity memory is now a key building block for storage in portable multimedia devices and a new rival in the mass storage market dominated by hard disk drives. In order to maintain its growth and viability in these markets, ever denser devices are needed and that means changes in device structure.

In September, Samsung introduced a SONOS-like structure called charge-trap flash (CTF). Its CTF-based NAND chip should be more reliable than traditional flash because it reduces cell-to-cell interference that can make bits harder to read.

Samsung refers to the total structure as Tanos, which comprises tantalum (a metal), aluminum oxide (a high-k material), nitride, oxide and silicon layers. Using a Tanos structure marks the first application of a metal layer coupled with a high-k material in a NAND device. Samsung now claims its charge trap flash technology will allow it to more easily scale NAND down to 30nm and even 20nm — which would yield a 256-Gbit chip.

A few months after Samsung, Taiwan's Macronix International said it was ready to test its Bandgap Engineered SONOS (BE-SONOS). The company will produce a 2 gigabit test chip this year using 75-nanometer technology. It expects commercialization will take place at 45-nanometer, sometime around 2010.

Toshiba said its new approach will bump up density without substantially increasing the chip's footprint because the array increases in direct proportion to stack height. "For example, a 32-layer stack realizes 10 times the integration of a standard chip formed with the same generation of technology," the company said.