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Message: Re: FLASH: Spansion, Intel, STMicroelectronics

"The two main architectures for handset memory subsystems are NOR plus RAM and NAND plus RAM, although a combination NOR plus NAND plus RAM is gaining acceptance in high-end phones, to take advantage of the strengths of both NOR and NAND. NOR-based phones use "execute-in-place" (XIP), while the NAND alternative uses "code shadowing."

For each approach, RAM is included for working memory, whether it's SRAM, Pseudo SRAM or DRAM. The essence of XIP, as the name implies, is that code can be executed in place, with some SRAM buffering required. Code-shadowing architectures involve heavy copying of code between the NAND and Mobile SDRAM. XIP is a proven architecture with fast code execution from NOR and no RAM overhead, whereas code shadowing uses a new architecture (both hardware and software), with fast code execution from the DRAM, but resulting in performance issues with RAM overhead and paging slow-down. Power consumption also becomes an issue with code shadowing, compared to XIP, which uses less power during operation."

http://www.embedded.com/showArticle.jhtml?articleID=165701775

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"with some SRAM buffering required. " 

What the comment is referring to, is what e.Digital does, "with some" means very little. The explanations for XIP from NOR,  are for reads only. How do you modify data within the flash when its needed? If you want to utilize the NOR with more utility needing write, you need a working memory. The XIP process being explained is for a one way usage only.  The OS utilized in conjunction with NOR for utility purposes,  if you want it,  will determine the size of the working memory.

For e.Digital,  for both read and write,  the working memory can be matched too as little as  one single  read/write block,  or what ever the device design requires...The system also operates independent of the erase blocks. For this, it does not need large working memory. 

 e.Digital offers a condition for both read and write with very tiny RAM resource,  or high speed cache.

For NAND,  they offer the same circumstance......they do not utilize a Code-shadowing architecture.

They have the ability to manage both types......

At some point, this is all going to come to a climax with e.Digital standing dead center,  patents in hand.

doni

 

 

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