Recently, at the International Solid-State Circuits Conference (ISSCC 2024), TSMC officially announced its use for high-performance computing (HPC), a new packaging platform for artificial intelligence chips, this technology is expected to increase the number of transistors in chips from the current 100 billion to 1 trillion.

Kevin Zhang, Senior Vice President, Business Development, TSMC In his speech, he said that this technology was developed to improve the performance of artificial intelligence chips. To add more HBM high-bandwidth memory and chiplets for chiplet architecture, more components and IC substrates must be added, which can lead to connectivity and energy consumption issues.

Zhang Xiaoqiang emphasized that TSMC's new packaging technology uses silicon photonics technology to use optical fibers instead of traditional I/O circuits to transmit data. Another feature is the use of heterogeneous chips stacked on the IC substrate and hybrid bonding to maximize I/O, which also allows the computing chip and HBM high-bandwidth memory to be mounted on the silicon interposer. He also said that this packaging technology will use an integrated voltage regulator to handle the power supply.

TSMC says today's most advanced chips can hold up to 100 billion transistors, but new advanced packaging platform technologies can increase that to 1 Trillions of transistors. An integrated voltage regulator will be used in the package to handle power supply, but he did not say when the technology will be commercialized.

In addition, Zhang Xiaoqiang also mentioned that TSMC's 3nm process will soon be applied to automobiles.