I asked permission and was given approval to post this doc at the beginning of this year. The images are missing but have been provided through historical presentations. Sorry for the format and bold is mine.

POET’s Optical Interposer Platform

 

By Suresh Venkatesan, CEO, POET Technologies, Inc.

 

December 2018

 

Abstract: The era of “More than Moore” has extended to the Photonics world with POET’s Optical

InterposerÔ Platform, which facilitates the co-packaging of electronics and optics using wafer scale

packaging techniques in a single Multi-Chip Module (MCM). Simply put, Optical Interposers pave the way

for “photonics-in-a-package”. Based on its Dielectric Waveguide technology, POET’s Optical Interposer

provides the ability to run electrical and optical interconnections in a common interconnect fabric on the

same interposer chip at a micrometer scale. Hybrid Integrated Photonics Packaging (HiPP) enabled by the

Optical Interposer plays a critical role in improving electrical and thermal performance, power

consumption and form factor of the photonics sub-assemblies. The Optical Interposer currently forms an

integral part of POET’s hybrid integrated Optical Engines and leverages the manufacturing processes and

unique capabilities of its dielectric waveguides.

The Need for Speed and Capacity

In the ten years since the introduction of the smartphone, people have fundamentally changed the way

they communicate, socialize, and interact with each other and the data around them. Today, smartphones

and other such devices allow us to capture, create and communicate enormous amounts of content. The

explosion in data, storage and information distribution is driving extraordinary growth in internet traffic

and cloud services.

The expected growth in the networking and data communications market is the result of many factors,

among them being, the growth of wireless and mobile traffic (which will account for two-thirds of total IP

traffic by 2020), social media activity, the progression of video transmission, the ramp of imaging such as

virtual/augmented/mixed reality and 3D video, the continued migration to cloud storage, the propagation

of sensors feeding the Internet of Everything, and the evolution of big data analytics and machine

learning/artificial intelligence. These factors will continue to drive long-term increased demand for greater

capacity and higher speeds.

Impact on the Photonics Market

Photonics has traditionally been employed to transmit data over long distances because light can carry

considerably more content and data at faster speeds. Optical transmission becomes more energy efficient

as compared to electronic alternatives when the transmission length and speed increase. As a natural

consequence, optics are systematically replacing copper in much of the data center communication links.

Data center operators are increasing the size and scale of their facilities, while simultaneously looking to

component suppliers for solutions capable of providing higher data transmission rates. Within data

centers, data communications over distances of up to 2km have already been transitioned from inherently

lower speed copper cable to optical fibers. Furthermore, short reach communications, either rack-to-rack

 

 

or within the rack as well as those requiring speeds of up to 100G, are now increasingly being converted

from copper to optical cables.

Outside the data center, future 5G build-outs will drive speed and capacity requirements closer to the

user with significant reduction in latency. Compared to 4G, 5G technology standard offers much faster

download and upload speeds, minimum delay in data communication and processing, as well as much

higher density in device connections. 5G will enable advances in virtual reality, augmented reality,

autonomous driving, high-definition video, and the Internet of Things, among others. 5G networks require

substantial capacity expansion for base stations, which is driven by three factors: more spectrum, higher

density of base stations in each region, and higher spectral efficiency.

Photonic transceivers will represent a $25 billion market in 2025, according to Oculi, llc. The primary

segments for photonic transceivers are ethernet, wide area network (WAN) and dense wavelength

division multiplexing (DWDM), all of which are predominantly addressed by Indium Phosphide (InP)-based

optical technologies. The market for ethernet transceivers is forecasted to grow to $7.4 billion by 2025

with 100G driving a majority of the growth. Within ethernet applications, single mode transceivers based

on InP devices are forecasted to outgrow multimode transceivers based on Gallium Arsenide (GaAs)

devices by a factor of 6:1. Segmented by distance, the majority of growth is expected in the <10km

segment ($4.3 billion by 2025). The data throughput of backbone networks, metropolitan area networks

(MAN) and access networks are 100G, 40G and 10G per second, respectively. As a result of technological

innovation and increasingly higher requirements of 5G, the capacity of these three networks will be

gradually expanded to 400G, 200G and 25G in the next few years.

To process and manage the unabated growth in data traffic, new advances in photonics will be required

that provide a scalable architecture for both reach and speed, spanning from 500m applications inside the

data center to 10km applications required by 5G infrastructure. Furthermore, packaging developments

are needed that address optical-to-electrical interconnection as photon and electron conversion moves

to the level of the package and the chip.

POET’s Optical Interposer Platform

POET’s Optical Interposer extends the functionality of traditional electrical interposers (which are used in

silicon wafer-level packaging techniques) by adding a parallel lane of optical interconnections to an

electrical interposer. Optical Interposers enable the concept of “photonics-in-a-package” by eliminating

traditionally used micro-optics such as lenses, filters, prisms from the optical assembly and by further

simplifying fiber optic alignment and coupling.

Bill Bottoms, who co-chairs the Hetero Integration Roadmap (HIR) effort of the IEEE, recently told the EE

Times1 about System-in-Package (SiP):

"The greatest single breakthrough in the near term will be the integration of photonics into SiP products

and efficiently connecting these systems with optical signals to everything else," Bottoms said. "Longer

 

1 EE Times, August 24, 2018 “Mapping the Future of Electronics” by Dylan McGrath.

 

 

term, co-design, simulation, highly parallel manufacturing, SiP and interconnect standards as well as the

development of ensured reliability and security will be needed."

POET has enabled this breakthrough with its Optical Interposer. In fact, POET’s Optical Interposer is the

first practical implementation of a photonics system-in-package utilizing wafer-level packaging (WLP)

technology. POET’s Optical Interposer utilizes the Company’s proprietary dielectric waveguide

technology, demonstrating unique design and process capabilities, and enabling POET to manufacture an

 

optical communication fabric within the context of a traditional complimentary metal-oxide-

semiconductor (CMOS) process. Consequently, it enables a novel and differentiated extension to more

 

traditional electrical interposers.

The waveguides incorporated in POET’s Optical Interposers perform more than just waveguide

transmission functions. They act as gratings, splitters, couplers and allow for manipulation of the light

with built in functionality suited to the application. For example, POET’s 100G family of Optical

Interposers include gratings that both function to enable narrow line width operation of its light sources

and to perform critical wavelength division multiplexing (WDM) operations.

A Typical Electrical Interposer

 

Shown above is a typical cross-section of an electrical interposer – that enables a closer placement of

electronic chips and minimizes communication lengths.

POET’s Optical Interposer

 

In much the same way as the electrical interposer incorporates electrical passive functionality, the Optical

Interposer incorporates passive optical functionality. Furthermore, the interposer enables the conversion

of electrical signals to optical signals and the manipulation and transmission of these optical signals

outside the package.

POET’s Optical Interposer provides the following advantages when applied to conventional optical

transceiver modules.

 

ü Wafer-level integration into silicon

 

ü Waveguides formed and integrated with embedded passive optical components (spot-

size converters (SSCs), mux-demux, filters, waveguides) at chip level

 

ü Ultra-low loss waveguide dielectric with high coupling efficiency

ü Pick and place assembly and passive alignment of components

ü Elimination of lenses and active alignment

ü Athermal waveguide dielectric allows multi-channel scalability

ü Wafer-level hermetic sealing, testing and burn-in of active components to produce known

good die

ü Small form factor and platform architecture readily scalable

ü High frequency metal traces managed in the dielectric platform

ü Fully compatible with conventional CMOS processing allowing integration with complex

electronics at chip or module level

 

Compared to semiconductors, where packaging accounts for 10% of the final die cost, packaging and

assembly is generally 80-90% for a photonic die. POET’s Optical Interposer heralds a new approach to

photonics packaging and assembly that could allow more functionality to be integrated into a single

package, similar to the system-in-package (SiP) trends observable in the industry today. POET’s Optical

Interposers offers a disruptive approach that leverages existing high-throughput microelectronic tools and

techniques to assemble cost efficient and scalable single-mode optical components.

Scalable Transceiver Architectures

POET’s transceiver Optical Engine architectures, based on the Optical Interposer, involve the passive

placement of multiple optical die comprising of light source arrays, modulator arrays and detector arrays.

Wavelength determination and selection functions, previously supplied with additional chips, can now be

incorporated into the Optical Interposer at virtually no additional cost.

By utilizing both an external cavity laser and an externally modulated source, the Optical Interposer

architecture enables a low-cost structure for all of the current 100G standards – PSM4 MSA, CWDM4 and

LR4. The gain chip arrays, PIN arrays and modulator arrays are common across the architectures – with

the differences in the design of the gratings and the multiplexer/de-multiplexer on the Optical Interposer.

This dramatically simplifies the BOM and modalities that need to be manufactured/tested/qualified across

the different physical media descriptions (PMDs) for the different applications.

The Optical Interposer is agnostic to speed and is able to accommodate additional channels in a

straightforward, low-cost manner. Since there are no micro-optics involved and the need for active

alignment is been eliminated, the Optical Interposer can scale from 4 channels to 8 channels with only

small increments of size and cost.

This simplifies the transition from 100G to 400G in transceiver modules while maintaining an attractive

cost structure for transceiver module suppliers.

Cost

In today’s data centers, pre-packaged transceivers and other optical modules include discrete, widely

separated (large-pitch) components. Traditional “gold boxes” and off-the-shelf components are too

 

expensive for downstream data center proliferation; however, adoption of POET’s Optical Interposer-

based Optical Engines holds the promise of meeting the aggressive price targets of data center operators.

 

 

The cost structure associated with POET Optical Engines enables transceiver module costs to achieve

<$1/Gbps, a long sought-after goal of data center operators. POET’s Optical Interposers are based on

silicon, allowing the Company to leverage the know-how, best manufacturing practices, and massive

scalability developed for high-volume CMOS manufacturing and microelectronic assembly. This can help

drive costs down along traditional semiconductor growth and cost trajectories. Manufacturing POET’s

Optical Engines using the POET Optical Interposer approach improves costs along several dimensions,

including: (i) using only known-good-die assembly, which improves final yields; (ii) enabling wafer level

packaging, testing (and potentially burn in), which are all much lower cost compared to conventional

module assembly; (iii) fabrication of Optical Engines on large wafer sizes, for example 8” diameter (where

global capacity is in excess) or 12” diameter; (iv) using conventional silicon processing techniques to

fabricate passive devices in the dielectric at low cost and high yield.

POET Optical Engines can also be built using external cavity lasers or gain chips for optical transmission

and are typically lower cost to build and take less power to operate than the more expensive and more

commonly used alternative of Distributed Feedback Lasers (DFB) lasers. Such lasers require an expensive

process of writing gratings and regrowth of epitaxial layers in the manufacturing process. Gain chips also

provide greater reliability and longer life to optical systems relative to Distributed Feedback Lasers (DFBs).

Sub-$100 PSM4 modules and sub-$150 CWDM4 modules are possible through the cost savings afforded

by the POET Optical Interposer-based Optical Engines.

POET’s Optical Engines reduce the cost of any photonic application by roughly 50% – enabling a 100%

increase in typical product margins realized by its customers.

Optoelectronic Integration Within a Package

Because optics can transport more data at significantly lower power than electronic transmission, the

intent is to drive optoelectronic conversion as close to the chip and microelectronic packaging level as

possible. The data remains in optical form – leveraging high optical densities – until it enters the package

and interfaces with the optical components within the Optical Interposer. At this point, the data is

converted from photonic to electronic format to undergo computation, storage, redirection, etc., by

conventional logic Integrated Circuits (ICs). Optical Interposers make possible the running of electrical

and optical interconnection fabrics within the same package or chip on a micrometer scale.

Outside the data center, optical transceivers are used in transport, enterprise, carrier routing and

switching markets. Within the data center, transceivers are located within each server and attached to

the edge of the board. This arrangement contributes to extra distance between the optical components

and the network switch or processor. This extra distance requires that re-timers be employed to

recondition the electronic signal (sometimes multiple times) before the signal can reach the edge of the

board. Significant simplification of the Input-Output (IO) designs and significant reductions in power can

be achieved if the optical components can be brought closer to the source of the data. POET’s Optical

Interposer enables optical components to be integrated in closer proximity to the source of the data, thus

bypassing today’s standard transceiver housings.

 

 

Wafer Scale Module Assembly

The advancements in semiconductor technology has created chips with transistor counts and functions that

were unthinkable a few years ago. Portable electronics, as we know it today, would not be possible

without equally exciting developments in Integrated Circuit (IC) semiconductor packaging. Driven by the

trend towards smaller, lighter, cheaper and thinner consumer products, smaller package types have

been developed. The smallest possible package will always be the size of the chip itself. Semiconductor

packaging technologies therefore evolved to converting the chip into the package – using what is now

largely known as “wafer level packaging” or WLP.

All semiconductor die, whether electronic or photonic, need to be packaged. The evolution of the

silicon industry from a packaging perspective has roughly tracked the following trajectory:

1. Wirebond Packages: These were the earliest and still often used form of electronic packages.

Each die is individually placed into its package, wire-bonded to the periphery pads and sealed.

This package is then placed on a printed circuit board. The figure below illustrates this.

 

The equivalent of such a packaging approach for photonics is shown below. This is how photonics

packaging is accomplished – and over 90% of photonics packaging and modules are still produced in this

fashion.

 

 

2. Flip Chip Packaging: In order to reduce size and to improve performance, a new class of

packaging technology was introduced in the late 1990’s, called flip chip packaging. With flip chip

packaging – the die are still mounted individually to each package, but instead of using wire

bonds, the die are connected to the package with what are called “solder bumps”. A pictorial of

this is shown in the figure below.

 

3. Multi-Chip Module (MCM): The next significant innovation and extension of packaging was to

integrate / place multiple die within a single package. This is called a multi-chip module (MCM)

and was created in the early 2000s as the need for increased density, improved performance

and reduced form factor became acute. In a multi-chip module, multiple chips are placed within

a single package. This is illustrated in the figure below – three die are shown placed in a MCM,

which is then placed on the printed circuit board (PCB).

 

4. Wafer Level Chip Scale Package: The MCM trend continued for the better part of a decade but

starting in the early 2010s, the continued shrinking of form factor for mobile devices in particular

drove the need for significantly more innovation. Instead of first assembling the chip into a

package – a process done individually at die scale – the path was to “convert the chip into a

package”. In this method, the “package” is effectively created over the die using wafer level

processing techniques and this method came to be called Wafer Level Packaging (WLP). The

major benefit of WLP is that all package fabrication and testing is done on wafer. The cost of WLP

drops as the wafer size increases and as the die shrinks. With integration, and specifically, by

embedding multiple die within the same package and with the use of innovative packaging

architectures, form factor can be reduced even further. The technical benefits of WLP are

numerous, substantiated, and increasingly difficult to ignore: 1) better reliability performance 2)

more functionality and higher levels of integration through multi-chip embedding and complex

architectures; 3) form factor reduction via innovative architectures; and 4) absence of substrate.

For these reasons, the semiconductor industry will witness the substantial and widespread

adoption of WLP technologies in the coming years.

POET’s Optical Interposer technology provides the equivalent of a wafer level packaging for optical

modules and sub-assemblies. The result of utilizing POET’s Optical Interposer technology is the creation

of optical modules or sub-assemblies at wafer scale, where by 100’s to 1000’s of complete optical modules

are created on a single wafer, bringing the economies of scale of silicon packaging to the world of

photonics.