I was reading a white paper from Cisco earlier this morning on silicon photonics in pluggable optics (I know, this sounds like the kind of read that puts you to sleep quickly..).

I am not a technology expert, but I understand directionallly the significance of co-packaged optics based on research I've done.  It's still not clear to me how POET has created "more lanes" and a resulting higher transfer rate than Cisco is capable of achieving.  Regardless, I am confident that POET has created something unique, and that there is a strong market for the technology.  (I am likely losing credibility with every word.  Sorry.  I'm just open an honest to a fault).

What struck me as highly valuable for POET is this paragraph concerning wafer-level testing and module yield (copied below).  To me, in layman's terms, what this means for POET is that they can easily validate their technology with integration partners and, more significantly, once the tech has been validated there is a high level of assurance that the ultimate integrated solution will be bug free.  Mass production can occur at an accelerated rate, and the probability that we, as investors, will wake up one morning to learn that "whoops, it broke" is extremely low.  Dumbing this down further, once a partner says "it works", we will quickly see revenues that will grow exponentially without risk of a major downturn in the sp.  This is significant.  I've work in the tech industry my entire career, and I know first hand how bugs and unforeseen issues can disrupt a business.  I read this paragraph as indicating that our risk is low.  I'll copy a link to the entire white paper below the copied paragraph.  Also interested in comments from the tech savy members regarding your impressions of the articule and the implications for POET.  (White paper is 2 years old..)

Wafer-level testing and module yield

Silicon photonics brings additional benefits along a different axis: reliability and repeatability. The design process for the optics follows a very similar workflow used by a traditional “fabless” electronics company. By defining and compiling the designs of the photonics devices into a photonic device library and design kit, the final design can be fully defined and then etched into silicon by the fab. This results in much less variability in performance than traditional optics that can be affected by later module assembly steps.

The maturity of lithography and wafer etching that is used by the silicon fab allows for well-defined precision and repeatability of the components. This means that statistical models and simulations can help understand and fully determine the performance of the transceiver up front during the design process before material is built. And of course, physical parts can be built and measured to corroborate the accuracy of simulation results. In this way, design-related issues can often be detected and corrected early in the product life cycle. 

Once the design is out of fab, there is another unique advantage that comes into play with silicon photonics. It becomes possible to perform wafer-scale testing on the photonics devices before they are diced into individual chips or built up into a module. This results in several important benefits. If there are any failed parts, they can be detected very early on in the build process. The bad die can be mapped and prevented from getting built up with other modules, thus avoiding waste of other components by using only known good die. This has a positive effect on overall yield fallout. This highly testable manufacturing flow and repeatable design performance help to bolster the reliability of the device.

https://www.cisco.com/c/en/us/products/collateral/interfaces-modules/transceiver-modules/silicon-photonics-wp.html