In keeping with the design flexibility we can see that the POET platform allows for the silicon substrate to be utilized for monolithically integrated electrical devices. If we examine the following POET patent you will observe a number of embodiments which include electrical devices that are monolithically integrated. These electrical devices are similarly identified in the embodiments below as shown for 7A and 7B. transistor arrays 764 in the substrate 710, are used for signal processing, signal conditioning, signal generation, memory, and computation

https://uspto.report/patent/grant/10,551,561#D00008 

7A, 7B, 

FIG. 7A-7B show cross sectional schematic views of embodiments of integrated planar waveguides on a substrate with interconnect layer and integrated electrical devices in the substrate in accordance with the inventive process: (A) without surface mounted optical or electrical devices and (B) with surface mounted optical or electrical device;

 integrated electrical device 764…

In some embodiments, integrated electrical device 764 in the underlying substrate 710 is a transistor, capacitor, resistor, inductor, or other electrical device. In other embodiments, integrated electrical device 764 is a p-channel metal oxide semiconductor (PMOS) transistor, an n-channel metal oxide semiconductor (NMOS) transistor device or array of one or more of these devices. In some embodiments, the electrical device 764 is an array of transistor devices based on complementary metal oxide semiconductor (CMOS) technology. In some embodiments, transistor arrays 764 in the substrate 710, are used for signal processing, signal conditioning, signal generation, memory, and computation

8A, 8B,

FIG. 8A-8B show cross sectional schematic views of embodiments of integrated planar waveguides on a substrate with interconnect layer and integrated electrical devices in the substrate in accordance with the inventive process shown with interconnections between top surface mounted device and integrated electrical devices in the substrate: (A) shown without the top mounted optical or electrical devices in place, and (B) with top mounted optical or electrical device; also shown is the position of an optical fiber relative to the planar waveguide in an embodiment;

 9C, 9D,

FIG. 9A-9D show cross sectional schematic views of embodiments of a substrate with interconnect layer: (A) with inventive dielectric stack mounted via bond pads to the substrate as a discrete optical waveguide component, (B) with inventive dielectric stack mounted to the substrate as a discrete optical waveguide component and aligned with discrete optical and electrical devices, and aligned to an optical fiber, (C) with inventive dielectric stack mounted to the substrate as a discrete optical waveguide component, for which the substrate contains integrated electrical devices, and (D) with inventive dielectric stack mounted to the substrate as a discrete optical waveguide component and aligned with discrete optical and electrical devices, and aligned to an optical fiber for an embodiment in which the substrate contains integrated electrical devices;