Note that Suresh will be sharing the stage with Intel’s Robert Blum at ECOC 2022. You may recall that Robert Blum has been quoted in a past POET presentation identifying needs for optical integration. 

The European Conference on Optical Communication (ECOC) is the continent’s largest event in the field and one of the most prestigious and traditional events on optical communications worldwide.

Hybrid integration of III-V devices with Silicon-based waveguides (Si, SiN, SiO2)

Details are subject to change.

• Organisers

• Hélène Debrégeas, Almae Technologies, France

• Lucas Soldano, POET Technologies, USA

• Day & Time

• 22.09.2022, 13:30 – 15:00

• Location

• Room Delhi

• Description

• The model of photonic devices has been evolving from standard packaging to photonic integrated circuits with more efficient and low-cost coupling solutions, compatible for ultra-dense integration. Multiple developments have been done on photonic integrated circuits, either fully on InP platforms mainly for active devices (lasers, high-speed modulators, photodiodes, …), or with Silicon Photonics (passive devices, high-speed modulators, photodiodes, …). But to make the best of both platforms in terms of performances and economic model, many laboratories or companies develop hybrid integration of III-V materials and Silicon-based devices (with Si, SiN, or SiO2 waveguides).

• This workshop will focus on the solutions for this hybrid integration, and will present the different technologies to couple light from III-V material to Si-based waveguides. Firstly, heterogeneous integration where III-V lays directly on top of Si-based waveguides with evanescent coupling. Secondly hybrid integration, where the III-V device is butt-jointed to Si-based waveguides, with various alignment techniques and waveguiding approaches. Thirdly, it will present emerging technologies still in development, their challenges and potential, such as transfer printing or direct growth in Si.

• The comparison will not only be on the technical / performances point of view, but as well on the business aspects, by analysing the business model, versatility and compatibility with multiple suppliers or external foundries, process tolerance to improve yield and costs. Presenters will explain what drove their choices, what are their main applications today and how they foresee future evolutions.

• Programme

• 13:30 – 13:50:   Robert Blum, Intel, USA

• 13:50 – 14:10:   An overview on thick-SOI Silicon Photonic platforms and integration roadmap at VTT, Giovanni Delrosso, VTT, Finland

• 14:10 – 14:30:   Hybrid Integration Platform for Co-Packaged Photonics Using POET’s CMOS Based Optical Interposer, Suresh Venkatesan, POET Technologies, USA

• 14:30 – 14:50:   Hybrid integration of III-V semiconductors on silicon, Dries Van Thourhout, Ghent University - IMEC, Belgium

• 14:50 – 15:00:   Discussion

• Speakers

• Speaker 1: Robert Blum, Intel, USA

• Short bio: Robert is head of silicon photonics strategy at Intel Foundry Services.

• Speaker 3: Suresh Venkatesan, POET Technologies, USA

• Title: Hybrid Integration Platform for Co-Packaged Photonics Using POET’s CMOS Based Optical Interposer

• Abstract: Dr. Suresh Venkatesan will present a unique hybrid integration platform for wafer scale passive assembly of electronics and photonics devices using a CMOS based optical interposer. The POET Optical Interposer enables seamless communications between electronics and photonics chips that are assembled on standard 200 or 300mm silicon wafers using visually assisted passive flip chip bonding techniques. This unique integration platform is the first such platform in the industry adapted to directly modulated lasers and enables the world’s smallest single chip Transmit/Receive Optical engine for 100G-400G optical engines.

• Short bio: Dr. Suresh Venkatesan is currently the Chairman & CEO of POET Technologies, Inc. Prior to joining POET Technologies in 2015, Dr. Venkatesan was SVP and CTO at GlobalFoundries, where he grew the 28 nm business from zero to $2B, and set the foundation for its 14 nm technology strategy. His 20+ years of semiconductor experience included many director of technology development and foundry roles within Freescale and Motorola. While at Motorola, he received three High Impact Technology awards and was inducted into the Scientific Advisory Board Associates (SABA). At Freescale, he was nominated as a Freescale Fellow. In 2017, he received the Outstanding Alumni award from Purdue University’s Electrical Engineering department for his contributions to the field of Semiconductor Technology. Dr. Venkatesan holds over 50 U.S. patents, and has co-authored over 50 technical papers. He has a Bachelor’s of Technology in Electrical Engineering degree from the Indian Institute of Technology (1987), and an MSEE (1988) and PhD (1992), both from Purdue University.