It is interesting to note that contained in this patent are applications where electrical devices are fabricated into the substrate. This demonstrates a very significant level of flexibility where low temperature and low stress disposition of the optical interposer stack allows for the underlying substrate to be processed for variety of applications. As such the platform would  be expected to allow both advanced nodes and larger 12 inch wafer  size. It should also be noted that substrate material flexibility also exists.

Electrical device 764, drawing 7a, 7b.

In some embodiments, the electrical device 764 is an array of transistor devices based on complementary metal oxide semiconductor (CMOS) technology. In some embodiments, transistor arrays 764 in the substrate 710, are used for signal processing, signal conditioning, signal generation, memory, and computation, for example. 

In preferred embodiments in which electrical or optoelectrical die are mounted onto the interposer 700, metal lines 726 are routed within the interconnect layer 720 to provide electrical connections for the devices in, on, or connected to the interposer 700, and to underlying electrical devices 764.

Electrical device 864, drawing 8a, 8b.

In some embodiments, integrated electrical device 864 in the underlying substrate 810 is a transistor, capacitor, resistor, inductor, or other electrical device. In other embodiments, integrated electrical device 864 is a p-channel metal oxide semiconductor (PMOS) or n-channel metal oxide semiconductor (NMOS) device, or array of one or more of these devices. In other embodiments, electrical device 864 is an array of transistors based on complementary metal oxide semiconductor (CMOS) technology. In some embodiments, transistor arrays 864 in the substrate 810 are used for signal processing, signal conditioning, signal generation, memory, and computation, for example.

In some embodiments, optoelectrical die 860 are connected to one or more electrical devices 864 via metal lines 826 in the interconnect layer 820.

Electrical device 964, drawing 9c, 9b.

 In FIG. 9C, interposer 900 is shown and includes substrate 910, interconnect layer 920, discrete waveguide component 965, and integrated electrical device 964.

In preferred embodiments in which optoelectrical die 960 are mounted onto the interposer 900, metal interconnects 926 are routed within the interconnect layer 920 to provide electrical and mechanical connections for electrical and optoelectrical devices in, on, or connected to the interposer 900, and to the underlying electrical devices 964

Integrated electrical device 964 in underlying substrate 910, in some embodiments, is one or more of a transistor, capacitor, resistor, inductor, or other electrical device, or array of electrical devices. In other embodiments, integrated electrical device 964 is a p-channel metal oxide semiconductor (PMOS) transistor or an n-channel metal oxide semiconductor (NMOS) device, or array of one or more of these devices. In yet other embodiments, device 964 is an array of transistors based on complementary metal oxide semiconductor (CMOS) transistor technology. In yet other embodiments, the integrated electrical device 964 is a bipolar transistor or an array of bipolar transistor devices. In yet other embodiments, the integrated electrical device 964 is a field effect transistor or an array of field effect transistors. In some embodiments, transistor arrays 964 in the substrate 910, are used for signal processing, signal conditioning, signal generation, memory, and computation, for example.

Electrical device 1164, drawing 11b.

 In an embodiment shown in FIG. 11B, substrate 1110 is shown with optional integrated device 1164. Integrated electrical devices 1164, in preferred embodiments, are connected to the interconnect layer 1120.