Good morning
All good dear Tpower.
There is one more story to demystify:
 Luxtera (now CISCO), IBM, STMicroelectronics and TSMC tech - please

Electronic-Photonic Integration

Three decades ago the work of Soref and Bennett signaled the dawn of silicon-photonics. To many, this meant that finally, optics would realize the same economies of scale that silicon-based microelectronics (especially CMOS) has enjoyed for decades. In this section, we take a look at the development trajectory of the silicon-photonic technology and the state-of-the-art in the capability of silicon-photonic processes available today (August 2018), in the context of the photonic interconnects as the flagship application for this technology.
Being able to create passive photonic devices in silicon, as well as affect the index of refraction through some current or voltage controlled mechanism are the necessary steps towards creating optical coupling, guiding, and modulating devices for photonic interconnects. However, the other key pieces of technology are the photodetector and the approach for integration with electronics, which determine the effectiveness of photon-electron conversion, and ultimately the energy cost, speed, and bandwidth-density and integration cost of the overall solution.

Indeed, the first commercial high-volume process, developed by Luxtera, attempted to address all of the issues above at the same time, by integrating the photonic devices in a then state-of-the-art 130 nm silicon-on-insulator (SOI) CMOS process. To yield good photonic device performance the process had to be modified with epitaxial Ge (Germanium) step for efficient photodetectors, as well as Si body partial-etch for passive and active waveguide structures. Small parasitic capacitances between transistors and devices were realized through monolithic integration, enabling energy-efficient, high-bandwidth transmitter and receiver components.
However, the process customizations and economic investment that led to having the improved photonic device performance, also prevented the technology from following the CMOS scaling trends of shrinking the device features every two years, and hence improving the transistor and system speed and energy-efficient. Furthermore, since interconnect speeds are scaling at an even faster rate of 4x every two years, this meant that the technology would soon fail to deliver the speeds required in new interconnect standards.

For example, it has been challenging for this technology to achieve 25 Gb=s modulation even into relatively small photonic loads such as ring-based optical modulators. To make a major impact, every process technology has to be qualified and available for high-volume production, and every additional process step complicates and slows down this process, further preventing the technology from following the mainstream scaling trends.
Similarly, IBM's monolithic photonic platform, which was implemented in a more advanced 90 nm node, took several years to qualify and achieve high-volume and availability due to process customizations. The issues with limited transistor performance and process qualification/availability recently have taken the manufacturers in a different direction. Both STMicroelectronics and TSMC have demonstrated hybrid integration of CMOS with Luxtera's photonic technology implemented in standalone photonic SOI wafers.

This approach decouples the transistor process development from the photonic process development and is seemingly very attractive since it allows the latest node CMOS circuitry to be used in conjunction with optimized photonic devices. However, this arrangement suffers from several issues which significantly limit its effectiveness to a narrow range of applications.

First, the micro-bumps used to connect the chip with transistors to the chip with photonic devices have limited scaling pitch (to about 40-50μm) and parasitic capacitances larger than 20 fF, which significantly impacts the speed and energy-efficiency of photonic interconnects.
Second, this connectivity arrangement limits the integration scenarios of photonics to 100G pluggable transceivers applications. To enable larger density and quality of electrical connections to the transceiver circuit chip, such as those needed in 400G pluggable and mid-board optics scenarios, the photonic process has to be modifed to add through-silicon-via (TSV)technology, further complicating the process and qualifcation. Alas, this multi-chip stacked solution is cumbersome for highly integrated optics-in-package scenarios. Photonic interconnects can achieve high volumes and remain the technology of choice for future system connectivity applications, if they can help address the bandwidth density and energy-cost limits of electrical I/O on large SoC chips such as network switches, graphics and multi-core processors (GPUs and CPUs) or field-programmable gate arrays (FPGAs). The integration and packaging approach have to enable both a low-energy, high bandwidth-density connection from the large SoC to the photonic transceiver chip, and a photonic connection out of the transceiver chip.  (as POET can do)

Cheers