The NA Tier 1. As most people here will recall early on Suresh talked about laser configurations that POET was working on for a customer. Pre-aligned groups of 4, 8 and up to 16 lasers designed for low loss insertion into a silicon photonics platform. And the thought process being this was to provide a good way for existing silicon platforms to be improved with CMOS friendly light source that have very low insertion loss and advanced thermal control. The heat generated by lasers in a silicon photonic platform is a problem that was highlighted by ether Intel or Cisco in the 24hr marathon session that we listened to last week. This also requires redundancy where laser failure can be tolerated N+1. It is something I touched on briefly with SV.

Bottom line though is that POETs low loss lasers configured for silicon photonics is a bridge to allow the transition to the full blown POET platform. An introduction to the mode matching capability and thermal control which is applicable to CMOS friendly micro fabrication. In other words it is an efficient means to insert a light source into silicon at low cost and high volume including lower energy requirements which of course is a very meaningful metric for the data center.

Now what does the customer need from POET to make this happen. That I believe would all be laid out in the tender process. It is a brilliant strategy once again demonstrating just how far ahead Suresh plans his moves.

My apologies to the forum for not being able to spend more time on this but I am very busy right now.