Aiming to become the global leader in chip-scale photonic solutions by deploying Optical Interposer technology to enable the seamless integration of electronics and photonics for a broad range of vertical market applications

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Message: Patent Granted

Important one! If I remember correctly, Suresh was quite proud of this breakthrough.

http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=%22poet+technologies%22&OS=%22poet+technologies%22&RS=%22poet+technologies%22

 

United States Patent 10,656,338
Lam May 19, 2020

Wafer-level optoelectronic packaging

Abstract

A wafer-level optoelectronic packaging method includes fabricating a pre-singulated wafer. The pre-singulated wafer has a plurality of sub-mounts. A first sub-mount of the plurality of sub-mounts includes an optical waveguide formed on a substrate, a multi-layered sub-mount boundary wall that is formed on the optical waveguide, and a v-groove that is external to the sub-mount boundary wall. A plurality of optical dies are attached to the corresponding plurality of sub-mounts, such that each optical die is aligned to the optical waveguide of the corresponding sub-mount. A cap-wafer including a plurality of caps is attached to the pre-singulated wafer to obtain an encapsulated pre-singulated wafer. The encapsulated pre-singulated wafer is diced to obtain a plurality of optoelectronic packages. The optical waveguide of each optoelectronic package serves as an interconnection conduit between the corresponding optical die and an optical fiber placed in the corresponding v-groove.

Inventors: Lam; Yee Loy (Singapore, SG)
Applicant:
Name City State Country Type

POET TECHNOLOGIES, INC.

San Jose

CA

US
 
Assignee: POET Technologies, Inc. (San Jose, CA)
Family ID: 1000004803508
Appl. No.: 15/802,009
Filed: November 2, 2017
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