Just to give an example of what is done in Ottawa let’s look at an example from the latest patent.

      In depositing step 1010, a stack of dielectric layers is deposited on the substrate to form the unpatterned inventive dielectric stack on the substrate, which is then patterned in patterning step 1020 to form the inventive interposer. In some embodiments, the patterned dielectric stack structure can be a section of waveguide aligned to an optical or electrical device, for example, for the transmission of optical signals to and from an optical fiber connected to the sub mount assembly. In other embodiments, these waveguides can include sections of the inventive dielectric stack that are patterned spot size converters, filters, arrayed waveguides, multiplexers, demultiplexers, gratings, power combiners, and the like. In yet other embodiments, these waveguides can provide part of a mechanical structure for the formation of hermetic seals. In yet other embodiments, theses waveguides can be a combination of one or more of these types of structures fabricated from the inventive dielectric stack structure. In yet other embodiments, the buffer layer and the layers of the repeated stack are patterned to form a filter, an arrayed waveguide, a grating, a multiplexer, a demultiplexer, a spot size converter, or a power combiner, and the like.

It is apparent when going through the patents that the platform can be applied to many future applications and just maybe will be applicable to the devices that Geoff Taylor designed:

A “substrate” as used herein and throughout this disclosure refers to, but is not limited to, a mechanical support upon which an interposer is formed. Substrates may include, but not be limited to, silicon, indium phosphide, gallium arsenide, silicon, silicon oxide-on-silicon, silicon dioxide-on-silicon, silica-on-polymer, glass, a metal, a ceramic, a polymer, or a combination thereof. Substrates may include a semiconductor or other substrate material, and one or more layers of materials such as those used in the formation of an interconnect layer.

 A “semiconductor” as used herein and throughout this disclosure refers to, but is not limited to, a material having an electrical conductivity value falling between that of a conductor and an insulator. The material may be an elemental material or a compound material. A semiconductor may include, but not be limited to, an element, a binary alloy, a tertiary alloy, and a quaternary alloy. Structures formed using a semiconductor or semiconductors may include a single semiconductor material, two or more semiconductor materials, a semiconductor alloy of a single composition, a semiconductor alloy of two or more discrete compositions, and a semiconductor alloy graded from a first semiconductor alloy to a second semiconductor alloy. A semiconductor may be one of undoped (intrinsic), p-type doped, n-typed doped, graded in doping from a first doping level of one type to a second doping level of the same type, and graded in doping from a first doping level of one type to a second doping level of a different type. Semiconductors may include, but are not limited to III-V semiconductors,