The article below “Packaging to Help Reduce Costs”  is linked from GlobalFoundries website. It is interesting because it essentially makes the case for POET. As we know GF has dropped 7nm and some of the rationale behind this move can be seen in this article. As a side note there are now only 3 companies that remain at the bleeding edge of node reduction.  The giant TSMC, Intel and Samsung.

I included the chart below to provide a snapshot of who dominates the market. As a point of interest the 8th ranking position has close ties with TSMC, is operating at maximum capacity and is in the process of buying GlobalFoundries fab 3E in Singapore.

 Packaging to Help Reduce Costs

While silicon advances – including dual work function metals in the gate stack, FD-SOI, and STT-MRAM – will improve performance, Letavic said packaging will play an equally large role, as companies move to link heterogenous devices made with the optimum process for each function. “I think after 20 years of discussion, 2.5D and 3D are going to be mainstream. We will see as much differentiation, if not more, from the packaging as you will from the silicon flows.”

Kevin Krewell, principal analyst at Tirias Research, said work being done with Advanced Micro Devices will give GF an advantage as companies put two or more chiplets in a single package. Earlier, AMD and Intel combined an AMD Radeon graphics processor with an Intel CPU in a single package. Now, AMD is boosting its Epyc server CPU line by using AMD’s Infinity Fabric interconnect technology. The forthcoming “Rome” server processor will feature multiple CPU and cache memory chip cores, linking those 7nm parts to a 14nm chiplet fabbed by GF that provides the I/O links to DRAM and the PCI bus.

By dividing tasks and using the optimum process for each function, chiplets connected over high-speed links will change how processors for several markets are created, Krewell said, noting that Nvidia, Intel and others are supporting high-speed chip-to-chip links.

“Using a mix of process nodes in a chiplet design, I do expect to see more of that. The I/O especially doesn’t scale well to 7 nm, and those functions take up a lot of space, even in 7nm. Sometimes it makes sense to put the I/O functions in an older chip. Historically, PC chip sets were made in an N minus 1 process, as part of a fab utilization strategy. Putting those functions in the right process node that can handle the I/O, where it is not as expensive per transistor, makes a lot of sense,” Krewell said.

Letavic said systems companies are demanding heterogenous integration using various forms of advanced packaging ranging from interposers, vertical through-silicon vias (TSVs), special laminates, fan-outs, and others. The strategy will also provide a boon to photonic connections, as opto-electronics can provide higher bit rates than some electrical connections can support.

Bob O’Donnell, principal analyst at market research firm TECHnalysis, said the chiplet strategy still has a ways to go before industry-wide standards are nailed down. Until then, companies such as AMD and others will use their own internal technologies to link multiple chiplets into SoCs.

“At a certain point, complexity becomes overwhelming and then companies start to look to simplify again. The problem is coming up with a fertile ecosystem among multiple vendors, allow packaging companies to package different parts from multiple companies. Those standards haven’t been nailed down yet.”

O’Donnell said the effort to use the optimum technology for each function is largely motivated by the high-cost of designing and fabbing large SoCs in a 7nm process, for example.

“The basic concept with chiplets, ironically, is that we are taking apart things that had been integrated in the past. The industry was able to integrate systems into fewer components, all the way down to SoCs that had almost everything in a single chip. But now, there is a slowdown because it is just so much harder from a technical perspective. The design costs at 7nm are extremely high, and the challenges from a manufacturing perspective are just crazy.”

Letavic said advanced packaging will provide benefits “at the chip level and at the system level. We are seeing it in the data center already. It is here to stay, and it will just get bigger.”

https://blog.globalfoundries.com/heterogenous-strategy-gaining-steam/