Killer video (pun intended)
From the first part of the video, speaker explains some of the challenges facing the industry. Seems Poet is addressing many of these (cherry picked, of course).
Interesting that Michael Lebby indicated a key challenge for the development of technology is in the lack of actual equipment available to test speeds of 100G and beyond. So, development is constrained by ability to test the technology you want to build.
The following challenges (among others) were identified in the short haul tel/datacom section. Feel free to comment, perhaps I've misinterpreted things or Poet's anticipated capabilities.
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Critical Challenges
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Poet?
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Advanced InP platforms with 4,8,16 channels for 400, 800 and 1600 Gps
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Check, in development (ie 16 lanes?)
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Lower power consumption
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Check
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Full integration of optics immediately adjacent to electronics
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Check
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Simpler optical coupling and non-hermetic packaging (ie or wafer level hermetic packaging)
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Check
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Wafer level test and assembly
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Check
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Technological Gaps
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Achieve $1/Gbps @ 400Gpbs
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Check?, check at 100Gbps
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Athermal designs where TE cooler are not needed
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Check
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Advanced, higher performing, lower cost
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Check
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packaging using chip on board, passive alignment, integrated optics and electronics
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Check
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Full hetero structure for more advanced monolithic platforms
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Check
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Simple optical alignment
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Check
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Technological Challenges for Product
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Wafer level test and assembly
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Check
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Demux and Mux for (C)WDM
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Check
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Improve yield
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Check
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Simple, cheap, low power, suitable for mass prod
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Check & Check
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