I was hoping someone else might tackle this one...lol

The short answer is no. POET’s interposer is designed to connect both optical and electrical circuits as an extension of the silicon chip from the edge. The technologies that are being worked on by industry connect from the top in a 3d bond (what Luxtera referenced as face to face bonding) to connect both electronics and photonics. One of the difficulties with this is that you have the Photonic Integrated Circuit on top of the silicon chip (ASIC) where temperature mapping and control are critical since photonics does not respond well to temperature variations. Of course POET's waveguides are athermal so a higher capability to withstand temperature change. But the typical hybrid design using bump bonds and optical TSV’s makes for a denser chip with reduced surface area for cooling.  As a result temperature of the PIC is directly impacted by the silicon in these TSV interposers and this results in the requirement for greater temperature control measures to limit refraction drift away from the wavelength operating band.

One of the key statements made by todays NR that makes it a little clearer for people is that POETs optical interposer is a CMOS-compatible package. So you are really talking about a different level of integration that is compatible with the processes used for CMOS fabrication. We still don’t have all the answers as to the process but I do like what is emerging.

Morning Star posted the following article in the off topic that might give a better understanding of how industry is attempting to solve these needs.

https://www.osa-opn.org/home/newsroom/2017/september/optical_interconnects_in_data_centers_what_s_next/

In the near term, companies, including Taubenblatt’s operation at IBM, are focusing on easing that power crunch through more efficient packaging of the optical links—that is, by placing the optics closer to, or even on top of, the electronic processing package. Taubenblatt showed examples of a number of on-package “optochip” prototypes that IBM has developed toward such better optical-electronic integration.

The POET solution is to place optics right at the edge of silicon within a few millimeters without 3d bonding but rather as part of the process flow removing coupling losses.