Just reading through, this is very interesting. The final paragraphs sum up the memory capabilities associated with the devices:

The configurable nature of the thyristor memory cell 100 as a static memory cell or a non-volatile memory cell has many advantages, including: 

The same footprint of memory cell is used. 

For all high speed functions, the SRAM operation is utilized. 

NV operation is only necessary for a sudden loss of power. Therefore there is no point is sacrificing speed to use NV `1`s and `0`s for all memory operations because the NV operations are somewhat slower than the SRAM's. Instead the NV operation is reserved only for those situations when it is required to protect from power loss. 

Therefore the kind of operation envisioned is one where the loss of power is monitored by on chip sense circuits. These circuits can operate with ns speeds and can detect power supply changes on microsecond time scales. Therefore the circuits continuously monitor the power supply. If a loss of power is predicted, then before there is a complete voltage drop, the NV writing mechanism kicks in and the state of the memory is captured. Then when power is resumed, the memory state is rewritten back to the SRAM mode and the operation continues. Thus NV operation is utilized only when required and the only overhead penalties are the power failure detect circuits and the NV write circuits. 

The thyristor memory cell 100 can also operate a DRAM cell as shown in FIG. 29. The states are the same as the SRAM of FIG. 27 but there is an additional state called the `store` state. Thus, after writing either a `1` or a `0`, and during the time that a read operation is not required (these represent substantial periods of time when neither writing nor reading are necessary), the cell 100 is powered down to a low voltage (e.g., approximately 0.6V). The charge in the modulation doped quantum well interfaces 117, 119 cannot escape by conduction because the components have been reduced drastically. Also recombination is essentially zero. Therefore, if a `1` is stored, i.e. the modulation doped quantum well interfaces 117, 119 of the thyristor device 111 are filled with charge, then they will remain filled for a long time. Simulations have shown that when the voltage is raised back to the SRAM `1` state after 1 sec, there is still enough charge left in the cell, to restore the ON state. That means the data has not been lost. If the store time exceeds some long time, say 2 seconds, then sufficient charge leaks away that a `0` will be obtained upon increasing the voltage. So a refresh operation is required periodically (e.g., once every sec) as shown in FIG. 30. The advantage gained is ultra-low power. The speed of read and write is identical to the SRAM. Clearly this DRAM has significant advantages which are: 

High speed operation, similar to SRAM cell. 

Selective operation of the cell as an SRAM cell or DRAM cell can be controlled by simply disabling the refresh cycle and the store voltage. 

The NV backup mode of operation is available here as well. 

Extremely low power operation is possible. 

Extremely high density as shown by the array layout (same as SRAM, NVRAM) 

No complex sense amps are required. The active of the thyristor device 111 is its own sense amp. 

Not limited by stored charge as in conventional DRAM. The thyristor device is an active device which can supply current instead of charge-active read. 

Finally, the DRAM, SRAM and NVRAM, have a photonic capability as well due to the optical writing and reading function capabilities of the device. 

This allows a linear array of thyristor memory elements 100 to be coupled to a single waveguide in order to detect and store bits of the optical signal carried by the waveguide. This is a perfect solution for the problem of optical data switching at the front of an optical router. These are photonic buffers. They can hold a frame of data (packet of bits) for several data cycles and then can be controlled to retransmit the data onto the network. 

The advantages of the thyristor memory cell 100 of the present invention are summarized in FIG. 31. 

There have been described and illustrated herein several embodiments of optoelectronic thyristor microresonator devices and systems based thereon as well as several embodiments of optoelectronic thyristor memory cell devices and systems based thereon. While particular embodiments of the invention have been described, it is not intended that the invention be limited thereto, as it is intended that the invention be as broad in scope as the art will allow and that the specification be read likewise. Moreover, while particular configurations have been disclosed in reference to particular thyristor microresonator devices and systems based thereon, it will be appreciated that other configurations could be used as well. Particularly, different quantum well active device structures can be used. For example, other active device structure with one or more modulation doped quantum well interfaces (e.g., a single n-type or p-type modulation doped quantum well interface) can be used. It will therefore be appreciated by those skilled in the art that yet other modifications could be made to the provided invention without deviating from its spirit and scope as claimed.