Aiming to become the global leader in chip-scale photonic solutions by deploying Optical Interposer technology to enable the seamless integration of electronics and photonics for a broad range of vertical market applications

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Message: Re: Rainer, wasn't there
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Jul 18, 2016 08:32AM

Yes, mystique, they showed an electron micrograph of integrated VCSEL and detector:

And they had a wafer of that stuff on display in the back of the room:

I don't know how difficult it is to integrate the electronics (transistors), but according to Suresh Venkatesan it is just "engineering, it is not innovation, it just takes time, and that’s what we’re working on. But I’m confident we’ll be able to get there, whether it’s going to be exactly in June or a few weeks here or there. I don’t see any challenges other than being focused 100 percent."

So they will get this accomplished sooner or later. Okay, it won't be sooner but later, since this was targeted for Q2. I expect them to be done really "soon" now.

Being a (software) engineer myself, I have experienced unforeseen impediments in projects more than once. They are nothing unusual if you are working on something new. As an engineer, you try to "foresee the unforeseeable": You don't know what the obstacles will be, but you know that they will occur, and you try to make an estimate on how much time they will cost you. The more experienced you are, the better your estimates will be – on average. However, will never be able to completely get rid of outliers.

Of course you will have to report to your customer or at least to your boss and explain the delay. I would expect the same from our management. They should say where we are today, what is still missing and what their updated estimate for completion is – barring any industry secrets, of course.

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