they might haven't had POET on the Radarscreen as they wrote the 2022 Roadmap ... Extract Photonics Roadmap only mentions SiP as solution....

3.10 Photonics

3.10.1 Introduction

The technology roadmap for data communication faces three challenges: achieving energy efficiency, scaling bandwidth to track processor roadmaps, and delivering low latency across systems, with exponentially increasing numbers of cores and processors.

The energy to move data today exceeds the energy to actually compute on the data itself, and this trend is expected to continue. For today’s highend systems, the fraction of power and cost for communications is comparable to processors or memory. Hence, data communication efficiencies must be sought at essentially every scale

from execution of instructions within the processor to the machine room floor. The fact that data communication is energy inefficient relative to computation and storage is only part of the problem. Systems increasingly require wider bandwidths, and the communication energy growing in a nonlinear way, with bandwidth, makes the problem even worse.

At the processor-memory level, tighter integration of memory and processor using 3D-ICs will address several of the communication challenges. Looking at past trends shows that evolutionary electronic solutions will neither reduce the data communications energy nor substantially increase the bandwidths, and certainly not both at the same time.

For communication beyond the individual socket, photonic interconnects offer the best path to lowbit transfer energies and the bandwidth scaling needed to track increases in CPU performance.[/b] Emerging silicon photonic technologies for interconnect fabrics have radically different performance characteristics when compared to existing CMOS electronics solutions. Silicon [b]photonics offers lower power and higher bandwidth density, and eliminates the link-length restrictions associated with electronic interconnects.

There are compelling arguments showing that silicon photonics is a foundational technology for highend systems. In the 2022 timeframe, high-end computing is expected to be in the exascale range. If an exa-operation application requires a communication ratio of only 0.04 bytes/operation, and each message goes on average through three hops (a very aggressive estimate), the total communication rate adds up to 40 TB/s, which at 4 pJ/bit per hop is about 4 MW, or 20 percent of the expected 20-MW system energy budget. Aiming at 4 pJ/bit per hop implies that the link energy has to be within 1 pJ/bit. Pervasive silicon photonics, all the way down to the compute elements, is the only technology that can reach this objective.

3.10.2 State of the Art

In high-end systems today, most optical interconnects use VCSEL-based transmitters, large area detectors, and multimode fibers. Several players are improving the cost effectiveness of these interconnects through simplifications in packaging and by increasing their bandwidth with improvements in VSCEL technology.

Silicon photonic transmitters with limited wavelength division multiplexing (WDM) capabilities have been demonstrated by several companies (such as Luxtera, Intel, and IBM) by using MachZender-based modulators. Since these devices exploit a weak effect to modulate the light, they have to be relatively large in silicon real estate,

which leads to high power requirements and limited scope for integration. Alternate approaches using resonant structures such as micro-rings as modulators have also been demonstrated by several companies (such as IBM, Sun, and HP). These resonators are more compact and enable dense wavelength division multiplexing (DWDM), but tuning the resonators and matching them to an appropriate laser source remain unsolved technical challenges.

Finally, hybrid silicon ring lasers [Lia11] use rings of silicon waveguide as resonators and as a laser cavity stimulated by a layer of III/V material bonded to

the silicon. As the laser’s wavelength is determined by cavity geometry, several highly compact lasers in a range of wavelengths can be formed on the same substrate, simply by varying the diameter of the resonant cavity. Samples of these devices have been shown to be capable of direct modulation at 10 Gbps. The directly modulated ring laser has several advantages: no requirement for an external laser source and optical power distribution, a greatly simplified tuning, and power proportionality (the devices can be powered off when not in use).

3.10.3 Challenges

While limited WDM is possible with VCSELs, the cost of such links is still proportional to the bandwidth, as each additional wavelength requires additional components. Silicon photonics has the potential for much higher bandwidth density through WDM and lower power through the use of low-loss, single-mode fiber and waveguide detectors. With silicon photonics, bandwidth can be scaled by adding very compact transmitters and detectors to an integrated photonic die, at a minimal increase in the overall cost.

Although photonic interconnects are in principle more power efficient than electronic interconnects for rack-to-rack distances and beyond, the use of active optical cables (AOCs) has negated much of this advantage. The full benefit of optical interconnect can only be realized when the entire physical link path is designed for photonics.

A complete integrated photonic link requires detectors, optical drop filters, and a range of waveguide and coupling technologies to suit different applications, which in turn involves ecosystem and supply-chain issues that are being addressed. An additional problem lies in coupling light on and off the integrated photonic die: while several approaches have been shown (including tapers and grating couplers), significant challenges remain. Finally, all photonics device technologies require innovative packaging that allows large numbers of single-mode waveguide connections to be made between devices and subassemblies. The development of appropriate packaging and connector and waveguide technologies is an obvious area where additional development is necessary.

3.10.4 Where We Think It Will Go

The design of packet switches for processor networks is constrained by the bandwidth density available at the chip perimeter. As the connections to switches span distances ranging 10 cm to 20 m, the link-length independence of photonics is particularly attractive. For these reasons, we believe that switches will be the first to exploit the benefit of close integration between high-density CMOS logic and silicon photonic communication. Figure 11 shows the time progression of photonics technologies, from active cables (single wavelength) to component-based photonics (CWDM) and on-chip interconnects (DWDM). DWDM silicon photonics will enable the development of very high-radix switch components while continuing to scale switch port bandwidths to track improvements in processor performance. Increasing the radix of switches allows low-diameter networks to be deployed with consequent advantages in latency, energy efficiency, and reliability. By exploiting silicon photonics, switch components with bandwidth up to 50 Tbit/s will become a reality. An attraction of high-radix network topologies is that the switches are distributed with the processors in a regular way, avoiding the wiring complexity of centralized switches. By incorporating additional logic in the switch fabric, the network will become more intelligent, and operations such as collective broadcast and reduction, whose importance increases with larger node counts, will become a reality through intelligent support in the network itself

3.10.5 Disruptions

A critical application of photonics will be to build highly energy-efficient router components that are interconnected optically, use CMOS electronics internally for packet processing and buffering, and connect to high-performance computing engines more efficiently than what can be achieved by co-packaging. Micro-solder bumps and face-to face copper bonds allow much smaller connections between devices, allowing arrays of closely packed transceivers to be bonded to the CMOS switch device. This increases the CMOS device’s effective chip-edge bandwidth, a performance bottleneck in today’s systems, and enables the development of higher port count switches without reducing port bandwidths. Higher port count switches further contribute to lower communication energy by enabling networks with a lower diameter to be constructed that require fewer retransmissions The availability of these new switches will enable whole new classes of network topologies that combine the ease of deployment of grids and meshes with the high levels of path diversity of logarithmic networks such as fat trees. Network topologies such as HyperX and flattened butterfly are ideally suited to high-radix switch components: with a high degree of path diversity, they have the potential to provide a highly resilient interconnect fabric scaling to millions of nodes.

3.10.6 Summary

Silicon photonics will be a fundamental technology to address the bandwidth, latency, and energy challenges in the fabric of high-end systems.

This area opens up the opportunity to build high-radix switches, with integrated support for important collective operations such as multicast barriers, reductions, scatter, and gather. In the 2022 timeframe, such a photonics-enabled high-radix switch could reach 64 to 128 ports, 640 Gbps per port, and 1 pJ/bit of link energy, which will enable connecting 1 million ports.

Bringing photonics inside chips has another effect: it gets rid of distance constraints, which in turns leads to flatter networks. A full photonics-based network is nothing but a giant supercomputer, where processing units are distributed geographically. This is going to change the software architecture of the switches in a telecommunications network and will eventually collapse telecom networks onto the computer’s inner network, the one connecting chips in a supercomputer. This will create disruption for telco manufacturers.