The emphasis on lowering power in everything from wearable electronics to data centers is turning into a perfect storm for the semiconductor ecosystem. Existing methodologies need to be fixed, techniques need to be improved, and expectations need to be adjusted. And even then the problems won’t go away.

In the past, most issues involving power—notably current leakage, physical effects such as electromigration, electrostatic discharge, RC delay and reduced battery life from inefficient designs—were dealt with by large, sophisticated engineering teams at leading-edge process nodes. When they couldn’t solve those problems the foundries stepped in and adjusted their processes. But with 55nm now considered a mainstream process for the Internet of Things, and most designs now using multiple cores and power domains—sometimes as many as 100 power domains per design—everyone is being forced to grapple with incredibly complex power techniques.

To make matters worse, process engineers can’t bail them out anymore. The manufacturing side already is wrestling its own power-related problems, such as shrinking gate oxides between ever-thinner wires, increasing dynamic power density at 16/14nm and beyond, and a massive and very costly effort to create next-generation processes to handle increasingly complex designs. That leaves even the best design engineering organizations are struggling to make everything work, within a very tight power budget, and on an increasingly tight schedule.

http://semiengineering.com/power-breaks-everything/