Semiconductor Technology Offers Exciting Possibilities, Feb 11, 2014

''In an ideal world, the latest devices would come equipped with compact, power-efficient, and ultra-connected supercomputers in a single chip. This one-stop-shop solution seems to be the goal of semiconductor companies and foundries alike. The latest integrated-circuit (IC) technologies are looking to integrate analog, digital, and RF components on the same chip. By doing so, they could more easily cater to the growing demand for commercial and military portable electronics while offering “big data” capability.''

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''To enable such features, however, these devices must implement the necessary hardware in a compact and power-efficient way. Many developed and newer technologies have been highlighted as solutions to this problem. For example, Fin field-effect-transistors-on-bulk (FinFETson-bulk), fully depleted silicon-on-insulator gallium arsenide (FDSOI GaAs), and FinFET-on-SOI are being considered by big players like GlobalFoundries, IBM, Intel, ST, Soitec, and many others. Of course, there are many manufacturing, cost, supply, and market factors that need to be detailed for engineers and companies to invest in a certain technology. First, let us consider the different MOSFET-based technologies.

Fully depleted MOSFET channel techniques offer a solution to the increased source-to-drain leakage caused by decreased channel size. Shrinking the channel size enables smaller transistor typologies, but increases the effects of leakage, parasitics, and the need for advanced fabrication techniques. High-performing RF technologies require the best of both worlds. If a MOSFET is designed to be fully depleted in the off state, the source-to-drain leakage will be reduced significantly enough to enable RF operation. The most commonly accepted techniques currently being explored are FinFET or SOI techniques (Fig. 1).

1. All leading high-end semiconductor technologies have to be weighed against cost benefits for certain industries and application needs. SOI may prove to have a cost and performance advantage over other silicon technologies. (Courtesy of GlobalFoundries)

FDSOI is a CMOS integrated technology that uses a highly resistive substrate—specified to be above 1000 Ω/cm—supporting a thin layer of silicon. This process adds some fabrication steps in terms of necessary development, but enables high-frequency capability by limiting loss through the substrate. FinFETs solve this leakage/parasitic problem by utilizing thin silicon fins, which project from the wafer for the MOSFET channel. FinFET technology can be adapted to either bulk or an SOI substrate.

The benefit of FDSOI over bulk is one of decreased junction capacitance, although cost is a factor here (Figs. 2 and 3). Up-front costs aren’t always the leading factor—especially in the case of RF technologies. The application and end device in which the RF technology will be implemented could have significant influencing factors on the viability of a technology. Another major concern is the availability of high-quality passive components that can meet the demands of current RF technology in very small sizes. With backing from companies such as Soitec, MagnaChip, GlobalFoundries, Peregrine, Apple, IBM, Altis, Qualcomm, TowerJazz, Skyworks, STMicroelectronics, and others, the choice for the next push of RF technology development appears to be FDSOI.

2. Comparing the figures of merit for RF-SOI and bulk-CMOS technologies demonstrates the performance advantages of RF SOI. Yet certain market factors, such as supply and cost, may limit the adoption of RF SOI in the short term. (Courtesy of Siotec)

The development of FDSOI technologies could very much impact the well-entrenched use of GaAs, which has played significantly in the commercial as well as military markets. Generally, GaAs offers very high RF mobility and a high breakdown voltage. Such characteristics lead to low RF losses, high linearity, and low-noise operation. Millimeter wave-frequency applications can take advantage of these factors. But the demands for some commercial markets involve increased integration.

3. Due to the highly resistive insulating layer in FDSOI MOS-FET transistors, leakage current is severely limited compared to bulk MOSFETS. This enables FDSOI-based technologies to operate at much higher frequencies than bulk technologies.

For low-power RF solutions, GaAs faces a significant limitation of GaAs: its lack of digital integration solutions. This failing is particularly felt in the handheld and portable device markets, whichare seeking a single system-on-a-chip (SoC) solution. The test and measurement equipment markets also are seeing demand for heightened integration of analog, digital, and RF technologies. As a result, a lot of research and development dollars are being spent adapting GaAs solutions to CMOS processes. For example, BiFET and BiHEMT involve the integration of several functions onto a single die for front-end RF-transceiver modules.

Often, the performance of low-power RF technologies is measured in terms of PA performance metrics and cost benefits. RF switches also should be considered when comparing potential technologies. As a result, developing a cost-effective solution with GaAs-comparable PA performance, digital/analog integration, and fast/linear switches is a must for FDSOI. Being able to offer a complete SoC solution while incorporating RF front-end technology could enable FDSOI to become a significant market player.

Currently, FDSOI resides at the 20-nm node with forecasts from IBS predicting a 14-nm node. The low leakage and relatively low die cost compared to bulk CMOS and FinFETs may make it a more attractive solution for cost-minded mobile-device manufacturers. As modern ICs require multiple voltage conditions for various power options, FDSOI’s ability to offer back-biasing implementations could give it a major advantage in the market. Back-biasing is the ability to adjust the transistors’ threshold voltage conditions. In FDSOI, that is done by tuning the biasing of a buried back gate under the MOSFET channel. According to the “IC Knowledges” study for Siotec, additional fabrication steps of up to 24 mask layers and 60 implants could be required to enable three or four threshold voltages with bulk MOSFETs. These additional steps wouldn’t be required for a back-biased FDSOI device.''