IBM has succeeded in depositing ultra-fast III-V nanowires suitable for transistor channels and other structures on silicon-on-insulator (SOI) substrates. Using a method IBM pioneered called template-assisted selective epitaxy (TASE), IBM says it has proven the concept by fabricating a variety of nanoscale Hall structures and multi-gate FETs.

Senior Researcher Heinz Schmid at IBM Research GmbH at Zurich Research Laboratory in Switzerland, asserted that template-assisted selective epitaxy laid a solid foundation to the integration of III-V materials with silicon, but cautioned about being overly optimistic about the new TASE method, noting that more development and optimization will be needed to fabricate transistors and other structures as complex as today's CMOS transistors, asserting that TASE presented "a very attractive prospect for the continued development of semiconductor circuits [using] large silicon carrier wafers on which multiple semiconductors with high mobility can be placed and co-integrated in an economically viable fashion."

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IBM Demos III-V on Silicon

My assertion: This could become competition to the POET techology, but see the text I highlighted.