Aiming to become the global leader in chip-scale photonic solutions by deploying Optical Interposer technology to enable the seamless integration of electronics and photonics for a broad range of vertical market applications
Message: SBIR Award for IR
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This is from the end of 2012.
At that time phase II status was active.
It might be they are building these at BAE as we speak.
AWARD DETAILS
AIR FORCE
| Proposal #: | F083-207-0757 | DoD Submission #: | F2-5016 |
| Phase: | II | Program: | SBIR |
| Proposal Title: | Monolithic InfraRed pixel structures enabled by Thyristor-HFET EO logic | ||
| AF Sol Topic #: | AF083-207 | DoD Technology Area: | Space Platforms |
| Solicitation #: | 08.3 | Gov't Managing Office: | RV |
| Agency: | AF | Gov't Sponsoring Office: | SMC |
| Topic Title: | Digital Optoelectronic Logic for Highly Interconnected Systems |
AWARD DETAILS |
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| Status: | Active (PII) | ||
| Amount: | 749904 | Contract: | FA9453-10-C-0003 |
| Start: | 1/4/2010 12:00:00 AM | End: | 12/30/2012 12:00:00 AM |
| Annual Report FY: | 2010 | ||
| Transition Success Story written? | Impact Story Submitted? No | ||
| HUBZone: | No | ||
| DTIC Rpt. Date: | DTIC Rpt. Num.: | ||
| DTIC Accession Number: DF837410 | |||
FIRM DETAILS |
| Firm: | ODIS | Socially & Economically Disadvantaged Business?: |
No |
| Address: | Three Corporate Drive |
Woman Owned?: | No |
| Veteran Owned?: | No | ||
| City: | Shelton | Disabled Veteran Owned?: | No |
| State: | CT | HBCU/MI: | No |
| Zip: | 06484 | HBCU/MI Name: | |
| Employees: | 8 |
CONTACT INFORMATION |
| Project Manager Name: | Dr. Jianhong Cai |
| Project Manager Title: | Senior Scientist |
| Project Manager Phone: | (860) 486-3466 |
| Project Manager Email: | laser242@hotmail.com |
| Corp Official Name: | Mr. Leon Pierhal |
| Corp Official Title: | CEO |
| Corp Official Phone: | (401) 338-1212 |
| Corp Official Email: | leepierhal@aol.com |
APPENDIX B |
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Abstract: IR imagers currently require hybrid read-out integrated circuits (ROIC’s)and additional separate AD converters (ADC) to provide transmittable data formats to digital signal processors (DSP’s). The DSP is currently dominated exclusively by CMOS technology as the only high density low power technology. New capabilities for IR imaging based on GaAs are being developed which have the potential for monolithic ROIC’s. However the advantage of the monolithic pixels increases enormously if digitization could also be realized within the chip. To this end, a special requirement is to develop and optimize the IR pixel simultaneously with the ADC. ODIS has identified a unique opportunity to implement novel multi-wavelength pixel designs together with a ÓÄ ADC in which the true ÓÄ performance can only be realized with a high speed decimator. At 60GB/s bit rates, the only solution to the decimator is EO logic. The pixel response is based upon intersubband absorption with CCD read-out transfer. The EO logic is based upon the unique thyristor properties. The combination of these functions monolithically will result in unrivalled IR capability. In this project, ODIS will optimize the pixel response and readout amplifiers in a planar technology platform that supports the EO logic needed for the decimation. |
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Benefits: The digital processor market is several billion dollars with steady growth potential based upon an expanding PC industry. The IR imager market will realize huge growth with the availability of monolithic pixel and ROIC combinations. A market opportunity thus exists to produce IR imagers supported by EO logic circuits. The market share for GaAs based digital products in the multi-GB/s range will expand dramatically. Digital and imaging products can now be added to a growing number of markets addressed by integrated optoelectronics including parallel optical data links, optical interface circuits, phased array receivers and other markets currently dominated by Si. |
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