Toronto, ON, and Storrs, CT, September 2nd, 2014
Synopsys, Inc. — a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems — to develop an advanced model and first Process Design Kit (PDK) of POET’s electrical devices (PET) targeting the 40-nm technology node ideally used for highly integrated systems-on-chip (SoC).

Wiki (https://en.wikipedia.org/wiki/Process_design_kit):

"A process design kit (PDK) is a set of files used within the semiconductor industry to model transistors for a certain technology for a certain foundry, different kinds of libraries to be used with design software tools

Typical PDK contains:

• standard cells library
• design rules (DRC rules)
• simulation model of transistors (typically SPICE)
• layout information (most commonly in GDSII format)"

SemiconductorEngineering.com (http://semiengineering.com/a-guide-to-advanced-process-design-kits/)

What Are PDKs?
"Process design kits consist of a set of files that typically contain descriptions of the basic building blocks of the process. They are expressed, algorithmically, as Pcells. These descriptions are stored in standardized Pcells libraries, design rules and rule constraints, schematics, SPICE model of transistors and other components, and layout information. They are used to describe, precisely, manufacturing process details for designers and design tools. The contents of the file will vary depending upon the target component, but they are all based upon the GDSII stream format.

PDK incarnations can involve any number of automated routine and rules. For example, arranging and routing programmable cells and analyzing the cell arrangement and interconnect wiring for optimum manufacturing. Other approaches can perform wire analysis and placement to prevent shorting. In other rules, the reliability of contacts and vias will be optimized by adding or subtracting additional metallization to the areas surrounding the contacts and vias. In still other cases, redundant contacts and vias may be adding to optimize efficiently manufacturability. Or, design and layout improvements can be made to cells in an iterative fashion.

PDKs will vary depending upon the specific device itself and their respective models. PDKs are generally specific to each foundry and the specific project or technology. Advanced PDKs contain specialized or proprietary data and/or functions, as well. The large foundries can offer a front-to-back integrated custom design environment that supports all major electronic data (EDA) vendors’ design flows. The major vendors include Synopsys, Lorenz Solutions, Helic, Cadence, Mentor Graphics, Ansys-Apache, and others.

The reason that PDKs have become the de-facto design approach to today’s semiconductor design is due to the complexities and ever-shrinking, ever-denser designs of new component technology. In a nutshell, PDKs automatically do the modifying and verification of the design modifications of complex semiconductor designs. This has antiquated the traditional top-down approach in favor of a new “parallel bottoms-up” verification approach that PDKs implement."

POET-Technologies:
"Q1-15 PET Foundation PDK (Process Design Kit) targeting 40nm (V 1.0) Design rules and parameters library models for PET process. Devices include complementary HFET and HBT transistor and a thyristor with both optical and electrical operation. "

Abel00:
Ok, so what does this mean? Well we're still working on our PDK, the 3rd party fab and Synopsis are finalizing the PDK right now, but it's not out yet, it's still a Millstone to be achieved Q1-15. The 3rd party Lab to Fab transfer that has been finalized was definitely crucial before this Milestone can be accomplished. Now they can test on a manufacturing scale(VLSI - Very Large Scale Integration) and this will give the necessary leftover information for the parameters & algorithms needed to input in PDK. The key thing to remember here, is that this PDK is essential to customers before they can do preliminary exploration of our process to make their Integrated Circuits(IC). Just like the Ring Oscillator is essential in proving proving proving performance statistics.

It's also very important to remember that the PDK timeline was extended becasue they wanted to add Novel Features!! That is excellent news.

Toronto, ON, and Storrs, CT, September 2nd, 2014:

The Synopsys toolset will be used for process technology development and design of nano-scale devices in POET’s III-V compound semiconductor process. Devices include complementary HFET and HBT transistors with high electron mobility performance, including a thyristor with both optical and electrical operation. These devices will form the foundation of POET’s technology that is able to integrate active optical circuitry, lasers, modulators, filters, detectors and electrical circuitry on a single die.

The PET PDK and process offers lower cost and simpler process fab options for applications that do not require the full POET optical feature set. Due to the high mobility inherent in III-V materials, PET technology is predicted to deliver performance, which could be equivalent to 3 to 4 nodes ahead of mainstream technologies. Further performance and novel capabilities will be enabled by the incorporation of in-plane optical intra and inter-chip signaling capabilities within the electrical technology. The PET/PDK is scheduled to be available at the end of Q4 2014 and will allow POET to provide detailed design information to industry fab partners and customers. This will enable pre-semiconductor design evaluation to integrate optical, analog and digital functions together. PET-based electronic devices represent a breakthrough in performance and power efficiency.

Toronto, ON, and Storrs, CT, October 22, 2014:

Operational Updates

"The Company is anticipating delivery of the 40-nm PET Process Design Kits (PDKs) by the end of the year. The Company is using Synopsys TCAD tools and services to develop the PET and POET PDKs. PDKs are used by 3rd party chip developers to create IP libraries that would be used to implement System on Chip (SoC) integrated circuits. Availability of the PDKs will enable early evaluation of the performance advantages of POET technology and design of IP required for SoC implementation. Daniel DeSimone, the Company’s Chief Technology Officer noted: “We are encouraged by our progress on the PDK development and our level of collaboration with the Synopsys team. This level of modeling is synergistic to our parallel efforts with our 3rd party foundry on the development of 100-nm and 40-nm process flow.”

The Company’s website and the corporate presentation have been updated to highlight the new targets set forth from the management team that reflect customers and market expectations. The value proposition of the company is strong with the new 40-nm feature size target predicted to operate 4 nodes better in logic performance and 3 nodes better in power consumption compared to Silicon CMOS. The density is expected to be comparable and possibly better, as POET requires less buffering and upsizing of logic cells. The POET process offers the ability to have digital, analog and mixed signals and optical devices on the same die or chip. Those capabilities would allow designs of complex systems and SoC (Systems on a Chip) to deliver innovations and integration that are impossible today with existing processes in the market. This process node also takes advantage of existing and mature manufacturing capabilities already available in the industry."

Toronto, ON, and Storrs, CT, January 8, 2015 – POET Technologies:

Milestone Updates

PET Foundation Process Design Kit (“PDK”) targeting 40-nm – Sentaurus modeling (a Synopsys tool) has been performed with new fabrication innovations to achieve controlled scaled device operation. These modeling predictions are guiding and confirming the device prototype development and testing. The PDK milestone has been moved to Q1 2015 so that the release incorporates the latest innovations currently being developed in the UCONN Lab and in parallel with the “3rd party foundry”.

“3rd Party Foundry” 40/100-nm Transfer – This “Lab-to-Fab” effort requires bringing up critical layers manufacturing capability in our “3rd party foundry” which enables more complex test structures. Significant progress has been achieved towards the completion of this milestone. The Company is very close to completing qualification runs for the flow in which the critical layers are performed at our “3rd party foundry”. This new flow will significantly accelerate completion and optimization of development on 100 and 40-nm foundation devices and associated proof of concept optical and electronic circuit structures.

Completion of Milestone – “3rd Party Foundry” 40/100-nm Transfer

The Company completed its “3rd Party Foundry” 40/100-nm transfer milestone consisting of completing the critical layers of the Transistor Fabrication Process. This flow process will allow the Company to generate more complex prototypes and test structures. As the POET process node size shrinks, this facilitates new industry innovations and furthers development work. This new epitaxial flow process includes new innovations in the POET prototype fabrication process. These innovations were necessary to continue the optimization work of the 100 and 40-nm foundation devices of our technology.

Toronto, ON, and Storrs, CT, February 10, 2015 – POET Technologies Inc:

Dan DeSimone, Chief Technical Officer noted: “This is a significant step for our “lab-to-fab” transition where this new flow at our “3rdParty Foundry” accelerates and adds repeatability and quality to our manufacturing process necessary for our next two significant milestones expected at the end of Q1: a 100-nm ring oscillator and a 50 GHz VCSEL.”