Fairchij: Regarding Rainer’s question. The whole beauty of the POET platform is just that. It is a platform and each chip has the same epitaxial layers so that every device produced by the POET structure can be organised on the same wafer. Memory and detection both use the thyristor structure...ie Imaging array utilizing thyristor-based pixel elements.

Thanks, Fairchij, especially for the link to the patent text. I should have known that the solution is of course thyristor-based. I think I found an answer here:

"The thyristor-based pixel elements as described above may be utilized in a variety of imaging arrays. For example, FIG. 7A illustrates a full-frame-type imaging array wherein the thyristor-based pixel elements are arranged in columns of CCD-type elements. The last pixel/CCD in each column is coupled to a horizontal CCD shift register. In this architecture, the charge stored in the pixel/CCD elements is transferred vertically to the horizontal CCD shift register for output therefrom." [Emphasis by me]

The PDF version of the US patent has Fig. 7A on page 13. I am too lazy to integrate it into this post. I think I will have to read the whole text one day in order to better understand it, but as of now I would say this is looking great, especially when getting back to my original question, i.e. everything's fully integrated and therefore at least one order of magnitude better than what the silicon firms are offering or trying to achieve. Huge opportunities here, IMHO!

Imaging – Powered by POET