Now this is interesting! EE Times has a new article

CMOS Image Sensors Surpassing Moore's Law

saying that growth and innovation for CMOS image chips is surpassing that of processors and memory, because everything from smartphones to tablets to medical equipment and automobiles needs them. The article cites analyst firm Yole Développement, which calls the pace of innovation surpassing Moore's Law. I think this exaggerated and inadequate.

Anyway, they are praising the fact that the CMOS imaging industry is close to replacing the through-silicon-via (TSV) between the sensoring chip and the memory chip by copper-to-copper (Cu-to-Cu) interconnects. Please note: Silicon imaging needs two chips: an imaging chip and a memory chip. They are connected (bonded) in one or the other way. This does not come cheap.

Fast-forward to POET. We know that POET has better imaging capabilities than silicon, because the images are much more low-noise. POET could thus benefit from the CMOS imaging boom, especially where high quality is required (in addition to the usual POET advantages we know about). Very nice poetential here!

A second item is integration, and here I am a little unsure. POET should be able to integrate imaging and memory into a single die, which would be a killer cost saver. On the other hand it is generally desirable to pack as much sensor pixels as possible as tigthly together as possible, so sensor cells and memory cells in the same die might interfere.

I don't know how POET's concept looks like in this respect, and I am very curious to know. Can POET maintain tight sensor packaging while monolithically integrating everything? Or has there to be some compromise? If yes, how does it look like? If no, how is this problem solved? What's the typical size of sensor cells? If they are very large compared to the memory cell, the latter's size won't matter.

Are people around here who can shed some light and enlighten me? Thanks you!