Aiming to become the global leader in chip-scale photonic solutions by deploying Optical Interposer technology to enable the seamless integration of electronics and photonics for a broad range of vertical market applications

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Message: Tech question for FJ, or anyone else

The corporate overview states "extremely low power savings 4 nodes ahead of silicon CMOS" shouldn't that be large or high power savings?

Also - "high performance applications - up to 10X faster than current technologies"

I am assuming that is for the 200nm, do they know what it might be at 40nm?

Thanks in advance.

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