I think it's interesting how the measurement metrics of the industry have changed over the years.

Take the personal computer or laptop CPU market for example.

For years, CPU's had been marketed by the speed of their clock cycle. Nothing gave a clearer sign of performance to the average user than a steady scale of rising numbers that equated to better performance. Intel led the way as the market leader. Even when others like AMD and Cyrix produced chips that outperformed or kept pace with Intel's offerings but at a much lower clock cycle, they adopted a naming scheme that closely tied the chips performance to what was expected by an intel chip of a certain clock speed.

When performance could no longer be conveyed accurately with the speed of the system clock, other system metrics were brought to the fore. Number of processing cores, L1/L2 onchip cache, number of transistors, and other numbers were used to aid in differentiating one chip from its competitors. The clock speed really doesn't mean as much with the silicon chips from the last decade. We really need more information to determine performance.

The latest yardstick that popped up for public use was the highlighting of the 'node' which is tied to distance between circuits but not exactly representative of the gate length of the individual transistors used in that node. I think the first reference to node size that I personally can remember is the 130nm node but that may be just because it was about that time that I started getting involved with building and troubleshooting PC's on a more regular basis.

But the last few years have really prooven that 3.2GHz means nothing with respect to computing performance without other information such as the number of cores, on-chip cache sizes, number of transistors (tied to node size), bus speed and size, and even the voltage the chip runs at.

Interesting article on node names and chip dimensions...

http://spectrum.ieee.org/semiconductors/devices/the-status-of-moores-law-its-complicated

So all this preamble leads me to my point and maybe a source of discussion for the board. What will be the metrics that POET uses for its technology when it finally makes it into the market?

I think clock speed is a given. Also high on the list would be the power efficiency. But I wonder what else will be marketed(or omitted from the marketing plans)

I personally think the speed of POET is being artificially throttled back to a reasonable leap over and above current market leaders. To me, it's the only reasonable explaination for the lowered expectation in speed based on numbers we were given at previous gate sizes(think GPS technology, where the most accurate was reserved for the military, and consumers were left with plus/minus 300ft). This would give a long life to both the technology and the fab. What if node size was something they didn't have to reinvest in for the next ten years? Is this the reason for the reduction to 40nm so quickly? Another question, is the 40nm barrier more of a fab requirement at this time, or is it customer demand?

Some interesting questions for sure. Also note PC's comments from the second news release today:

*********

"Mr. Peter Copetti, Executive Chairman Interim CEO concluded: "We now believe we have the right collaboration in place with Synopsys and our "3rd party foundry" to model our technology down to 40-nm and correlate our process to real physical device measurements. This should provide us with results needed to showcase our technology to potential customers at the optimum node for our platform. We expect synergistic benefits from having parallel operations with the same end target."

*********

From this statement we see 40nm is related to effort to correlate the POET process to real physical device measurements. I take this to mean that size matters, although I can't quite wrap my head around the reason why they can't stuff as many POET devices into whatever dimensions are required but at a 100nm node size. From everything we've learned so far, this should still outperform existing technologies.

Regardless of all the questions that may pop up as we watch this story unfold I think one thing is clear, POET will change the world of technology as we know it today. And the evidence is mounting that it will happen. The addition of Ajit Manocha was a watershed moment in my opinion, as so many have stated before. And now with the confirmation of the TCAD partner, Synopsys, more of the ducks are lining up.

So I look forward to the next year with anticipation in hopes of watching the reaction of all those in the industry that have been struggling to reach that next node in silicon CMOS development watch this small tech company attract the attention of the world. At that point all those that were given the chance to discover POET and passed on the opportunity will be, as the title of this post implies, in shock.

Green

PS. Even if you don't like the post I should get points for the corniest pun ever. :)