But there is no mention of PET in the Feb.24, Feb.11 NR, and this statement from Mar.4

POET is moving steadily towards the goal of 100-nm feature sizes for the transistors within the POET platform, and has stabilized feature definition at the sub-200-nm level. Short channel considerations are being addressed with new innovations, and the critical step of isolating source-drain and gate contacts with oxygen implantation is nearing completion. The 100-nm goal is matched to the state-of-the-art commercial III-V foundry capabilities and will demonstrate greater than 20x speed improvement together with lower power consumption by 4x to 10x, depending on the application, compared to silicon at smaller nodes.

I'm still confused if it is not POET being brought to 100nm.