I qoute from the news release and underline a relevant phrase:

POET is moving steadily towards the goal of 100-nm feature sizes for the transistors within the POET platform, and has stabilized feature definition at the sub-200-nm level. Short channel considerations are being addressed with new innovations, and the critical step of isolating source-drain and gate contacts with oxygen implantation is nearing completion. The 100-nm goal is matched to the state-of-the-art commercial III-V foundry capabilities and will demonstrate greater than 20x speed improvement together with lower power consumption by 4x to 10x, depending on the application, compared to silicon at smaller nodes.

This implies that the 100nm reduction is not yet achieved and suspect the speeds quoted are a conservative assessment of current achivements. Expect faster speeds when full reduction is achieved with milestone 8. If it is, and I have no reason to suspect it will not be then we will be in the realms of truly disruptive technolgy. GaAs is faster because of its basic atomic structure than doped silicon and if taken up by the industry generally, then the rewards can be truly described as vast.