So something doesn't make sense to me at all.

The news release stated:

"With transistor cut-off frequencies around 38 gigahertz for a 0.7-micron gate, the scaling is expected to produce 260-gigahertz transistors with commensurate improvements in circuit speed. "

Yet in oogee's statement yesterday (see below) he made it sound like reducing to 100nm would be just good enough to outperform Si CMOS. Si CMOS at 4Ghz is not even in the same ballpark as 260Ghz @ 100nm so why are you suggesting performance is the reason for going down to 100nm? From the news release you can conclude that even at 600 or 800nm it would still severely outperform Si CMOS. Why would they need to go down to 100nm just to outperform it? I was always under the impression that even at current scale (last year's scale)it already severely outperformed Si. Thats one of the main reasons we are all here, because the performance shouldn't even be comparable.

" What I think is really going on is that the company in question is willing to give POET time to demonstrate a chip that will outperform Si CMOS, which is stuck at under 4GHz. "