Here's my impression of Intel's stance and motivation with respect to POET.

First I'll share some background I've collected on Intel's problems and what I think might explain their attitude.

1) Intel's strategy: dominance by attrition

I think Intel has been waiting a long time to reach this moment. Below is a graph POET once had in their CP:

Intel's claim that Moore's Law is alive and well is true for them and Samsung (and possibly Ti) alone. If Intel can keep the whole "nm" race in everyone's consciousness for a couple of years, they will win the war as the other chip companies drop off for lack of cash. This is what Copetti highlighted when he referenced DARPA's MTO director. Intel needs to continue shrinking CMOS, and they need people to continue believing it will lead to higher performance to win a war of attrition.

But is the nm race worth pursuing?

2) Investment v. Performance - Diminishing Returns

Here's a chart and the link to the site hosting it:

http://www.extremetech.com/computing/116561-the-death-of-cpu-scaling-from-one-core-to-many-and-why-were-still-stuck

http://www.gotw.ca/publications/concurrency-ddj.htm

Clearly, by the statements Copetti has undertaken to refute, Intel wants to maintain the illusion that Moore's Law has a long life ahead. They are promising ever smaller gate sizes using convoluted 3D transistors on strained Si to cheat death. But the chart above shows that the number of transistors isn't leading to higher clock speed. The above link (below the graph) states that gains in performance do not come from clock speed; they have come from hyperthreading, multicore, and cache. Well if POET *can* produce processors exceeding 5GHz, they can also employ hyperthreading, multicore and cache improvements for further gains. The difference is that POET will have MASSIVE scaling opportunities which will not diminish as Si CMOS has for decades!

3) Secret Sauce (or Si CMOS @7nm < POET @ 100nm)

If Intel can foresee 7nm transistors with Si CMOS, how can we compete at 100nm?

Well from what I've read and understood (And there may be some misconceptions - I'm not an engineer) it has a great deal to do with electron mobilities. Here's a powerpoint which I found interesting, and an image from one of the slides:

http://www.sematech.org/meetings/archives/symposia/10348/pres/Keynote_03_TP_Ma_Final.pdf

As the chart shows, the electron mobility (second row) is multiples higher in GaAs than it is in Si. I believe this means that equivalent transistors in Si and GaAs will have dramatically different clock speeds with GaAs coming out on top.

There are also functional differences which I think make POET even faster than the electron mobilities would suggest.

Now, if you read the whole chart you might have noticed that the hole mobility is another story (third row). This is a known hurdle for the proliferation of III-V based transistors.

Here's one of the slides stating this fact:

This has been the only unanswered question for me and I currently have a request in to IR to explain this. POET has reported the n-channel clock speed in the high 30s and low 40s. The p-channel hasn't been reported as often and is only ~3GHz. Also, the n-channel has shrunk since the laser announcement while the p-channel remains 1um.

I hope to hear back soon and I hope to hear that POET's "secret sauce" is that the very low hole mobility has either been increased beyond what is known to be possible (such as what Si achieved according to this article). Or even better, I would like to discover that the p-channel speed has become a non issue due to the construction of POET complementary inverters. In other words, I hope they can confirm that the n-channel speeds are the ones that compare to CMOS.