@woundedknees

I can say I've read in multiple sources that GaAs electron mobility is much higher than in Si. This is not controversial.

I can also say that I've read conflicting accounts of hole mobility, with GaAs sometimes claimed to be even lower than Si. I believe this is the basis for the p-channel transistor.

It appears that since CMOS requires both p and n channel transistors connected in order that the transistors don't draw power when they are not being used (one blocks current while the other is open, or vice versa), both the p and n channel are needed.

Unfortunately, there are many things I don't know.

For one, are there other factors that determine the clock speed besides electron and hole mobility of the p and n channel transistors? I believe there are, but I don't know exactly what they are. This article says:

"Most III-Vs have very high electron mobilities, making them ideal for n–channel devices. But CMOS needs p-channel transistors too, and the hole mobility for III-Vs is too low - for many arsenides, it is actually lower than it is for silicon. Mobilities in silicon have improved through the addition of strain in the material, with the performance of the pchannel now approaching that of its n-type cousin. It will be interesting to see if the same trick will work for the arsenides"

So, I would like to know if POET is in any way special in this regard. Maybe the way they use the layers of doped and undoped material bends the rules and speeds up the p channel? Maybe these channels are connected in a unique way that negates the slower clock speed of the p channel? I can't answer this. I know that Lee S was much more impressed with POET's complementary inverter than he was with the laser announced in Dec. I'm assuming that something about POET rectifies the "problem with the holes"

So to answer your question (finally) I don't know for sure if POET's 100nm will be faster than Intel's 7nm Si CMOS processor. But realistically POET needs to beat CMOS and then some to get them to rethink the trek down to the 7nm virtual dead end. From that I assume POET is going to 100nm in order to do just that. Hopefully then we get bought out for an amount that lets us all quit our jobs:)

Just to support my assumption, here's a reminder of when Taylor had to say in the PCWorld article:

"OPEL only recently exited the R&D stage and hasn't tried to make itty-bitty transistors at Ivy Bridge's 20nm size, but the company claims that at 800nm, gallium arsenide processors are faster than today's silicon and use roughly half as much voltage.

"If you wanted to match the speed of today's silicon processors, at roughly a 3GHz clock rate, you wouldn't have to go all the way down to 20 or 30 nanometers," says OPEL chief scientist Dr. Geoffrey Taylor. "Heck, you could probably hit that at 200nm." And that's using planar technology, not 3D transistors"

I'm not sure how to reconcile the two paragraphs above. Is the first paragraph about the n-channel (with POET beating Si CMOS at 800nm) while the second is about the p channel (beating Si CMOS at 200nm)? If so, PET will utterly annihilate current CMOS at 100nm and any company not rich enough to follow Intel down the 7nm rabbit hole will be all over PET.