Aiming to become the global leader in chip-scale photonic solutions by deploying Optical Interposer technology to enable the seamless integration of electronics and photonics for a broad range of vertical market applications

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Message: POET performance data sheet, chip test bench marks, lab spec overview? ,

@Aves

Maybe that's what makes this particular point in time the most critical.

We have a nearly, but not quite complete, CMOS replacement and OEIC marvel with massive scaling potential that allows someone like Intel to conduct business as usual with existing equipment and a focus on srhinking transistors and then putting the 'O' back in POET by adding emitters and detectors for further performance gains.

At the moment only a handful of people on this Earth know how to make a POET wafer - the patents don't do it on their own. I'm sure these folks are legally locked down and can't transfer the technology themselves.

But when the fully integrated chip becomes avaiable, after the MS are complete, they don't need much besides some secret sauce type trade secrets to run with it on their own.

I fell that interested parties will see this as a ground floor opportunity to surprise the tech world being first to market with a new extensible technology.

***

In a somewhat related point I'm reposting the response to my question about lowball offers from Taylor, Tim from IBK (It might have been Mike, I can't remember who was there with us at that point on the lab tour), and Benadiba. It's interesting because even back then they seemed to be urgently awaiting the completion of both the VCSEL and complementary inverter: MS6. This is the clip where they say that the "complementary plus laser" might very well throw us into an auction scenario.

I've cued up the video to the relevant section, but for those who have not heard it it's worth listenting to the whole thing (and all of the fairchij recordings for that matter)

http://www.youtube.com/watch?feature=player_detailpage&v=B_fTMAcyf-4#t=498

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